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c50372298d
1. A delay slot filler that searches for valid instructions
to fill the delay slot with. Previously NOPs would always
be inserted into delay slots.
2. Support for MC based instruction printer added.
3. Support for MC based machine code generation and ELF
file generation. ELF file generation does not yet
completely work as much of the ELF support infrastructure
is still x86/x86-64 specific.
4. General clean up of the MBlaze backend code. Much of the
tablegen code has been cleanup and simplified.
Bug Fixes:
1. Removed duplicate periods from subtarget feature descriptions.
2. Many of the instructions had bad machine code information
in the tablegen files. Much of this has been fixed.
llvm-svn: 116986
71 lines
1.7 KiB
LLVM
71 lines
1.7 KiB
LLVM
; Ensure that all immediate values that are 32-bits or less can be loaded
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; using a single instruction and that immediate values 64-bits or less can
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; be loaded using two instructions.
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;
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; RUN: llc < %s -march=mblaze | FileCheck %s
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; RUN: llc < %s -march=mblaze -mattr=+fpu | FileCheck -check-prefix=FPU %s
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define i8 @retimm_i8() {
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; CHECK: retimm_i8:
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; CHECK: rtsd
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; CHECK-NEXT: add
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; FPU: retimm_i8:
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; FPU: rtsd
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; FPU-NEXT: add
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ret i8 123
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}
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define i16 @retimm_i16() {
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; CHECK: retimm_i16:
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; CHECK: rtsd
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; CHECK-NEXT: add
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; FPU: retimm_i16:
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; FPU: rtsd
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; FPU-NEXT: add
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ret i16 38212
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}
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define i32 @retimm_i32() {
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; CHECK: retimm_i32:
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; CHECK: add
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; CHECK-NEXT: rtsd
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; FPU: retimm_i32:
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; FPU: add
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; FPU-NEXT: rtsd
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ret i32 2938128
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}
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define i64 @retimm_i64() {
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; CHECK: retimm_i64:
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; CHECK: add
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; CHECK-NEXT: rtsd
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; CHECK-NEXT: add
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; FPU: retimm_i64:
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; FPU: add
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; FPU-NEXT: rtsd
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; FPU-NEXT: add
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ret i64 94581823
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}
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define float @retimm_float() {
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; CHECK: retimm_float:
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; CHECK: add
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; CHECK-NEXT: rtsd
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; FPU: retimm_float:
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; FPU: or
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; FPU-NEXT: rtsd
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ret float 12.0
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}
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define double @retimm_double() {
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; CHECK: retimm_double:
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; CHECK: add
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; CHECK-NEXT: add
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; CHECK-NEXT: rtsd
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; FPU: retimm_double:
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; FPU: add
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; FPU-NEXT: add
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; FPU-NEXT: rtsd
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ret double 598382.39283873
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}
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