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db43217a24
Currently we have a number of tests that fail with -verify-machineinstrs. To detect this cases earlier we add the option to the testcases with the exception of tests that will currently fail with this option. PR 27456 keeps track of this failures. No code review, as discussed with Hal Finkel. llvm-svn: 277624
69 lines
3.1 KiB
LLVM
69 lines
3.1 KiB
LLVM
; RUN: llc -verify-machineinstrs -march=ppc32 -mtriple=powerpc-unknown-linux-gnu -mattr=+altivec < %s | FileCheck %s
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;; This test ensures that MergeConsecutiveStores does not attempt to
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;; merge stores or loads when doing so would result in unaligned
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;; memory operations (unless the target supports those, e.g. X86).
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;; This issue happen in other situations for other targets, but PPC
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;; with Altivec extensions was chosen for the test because it does not
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;; support unaligned access with AltiVec instructions. If the 4
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;; load/stores get merged to an v4i32 vector type severely bad code
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;; gets generated: it painstakingly copies the values to a temporary
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;; location on the stack, with vector ops, in order to then use
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;; integer ops to load from the temporary stack location and store to
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;; the final location. Yuck!
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%struct.X = type { i32, i32, i32, i32 }
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@fx = common global %struct.X zeroinitializer, align 4
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@fy = common global %struct.X zeroinitializer, align 4
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;; In this test case, lvx and stvx instructions should NOT be
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;; generated, as the alignment is not sufficient for it to be
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;; worthwhile.
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;; CHECK-LABEL: f:
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;; CHECK: lwzu
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;; CHECK-NEXT: lwz
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;; CHECK-NEXT: lwz
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;; CHECK-NEXT: lwz
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;; CHECK-NEXT: stwu
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;; CHECK-NEXT: stw
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;; CHECK-NEXT: stw
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;; CHECK-NEXT: stw
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;; CHECK-NEXT: blr
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define void @f() {
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entry:
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%0 = load i32, i32* getelementptr inbounds (%struct.X, %struct.X* @fx, i32 0, i32 0), align 4
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%1 = load i32, i32* getelementptr inbounds (%struct.X, %struct.X* @fx, i32 0, i32 1), align 4
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%2 = load i32, i32* getelementptr inbounds (%struct.X, %struct.X* @fx, i32 0, i32 2), align 4
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%3 = load i32, i32* getelementptr inbounds (%struct.X, %struct.X* @fx, i32 0, i32 3), align 4
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store i32 %0, i32* getelementptr inbounds (%struct.X, %struct.X* @fy, i32 0, i32 0), align 4
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store i32 %1, i32* getelementptr inbounds (%struct.X, %struct.X* @fy, i32 0, i32 1), align 4
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store i32 %2, i32* getelementptr inbounds (%struct.X, %struct.X* @fy, i32 0, i32 2), align 4
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store i32 %3, i32* getelementptr inbounds (%struct.X, %struct.X* @fy, i32 0, i32 3), align 4
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ret void
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}
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@gx = common global %struct.X zeroinitializer, align 16
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@gy = common global %struct.X zeroinitializer, align 16
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;; In this test, lvx and stvx instructions SHOULD be generated, as
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;; the 16-byte alignment of the new load/store is acceptable.
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;; CHECK-LABEL: g:
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;; CHECK: lvx
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;; CHECK: stvx
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;; CHECK: blr
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define void @g() {
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entry:
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%0 = load i32, i32* getelementptr inbounds (%struct.X, %struct.X* @fx, i32 0, i32 0), align 16
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%1 = load i32, i32* getelementptr inbounds (%struct.X, %struct.X* @fx, i32 0, i32 1), align 4
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%2 = load i32, i32* getelementptr inbounds (%struct.X, %struct.X* @fx, i32 0, i32 2), align 4
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%3 = load i32, i32* getelementptr inbounds (%struct.X, %struct.X* @fx, i32 0, i32 3), align 4
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store i32 %0, i32* getelementptr inbounds (%struct.X, %struct.X* @fy, i32 0, i32 0), align 16
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store i32 %1, i32* getelementptr inbounds (%struct.X, %struct.X* @fy, i32 0, i32 1), align 4
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store i32 %2, i32* getelementptr inbounds (%struct.X, %struct.X* @fy, i32 0, i32 2), align 4
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store i32 %3, i32* getelementptr inbounds (%struct.X, %struct.X* @fy, i32 0, i32 3), align 4
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ret void
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}
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