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fe9adb9248
This patch corresponds to review: https://reviews.llvm.org/D23155 This patch removes the VSHRC register class (based on D20310) and adds exploitation of the Power9 sub-word integer loads into VSX registers as well as vector sign extensions. The new instructions are useful for a few purposes: Int to Fp conversions of 1 or 2-byte values loaded from memory Building vectors of 1 or 2-byte integers with values loaded from memory Storing individual 1 or 2-byte elements from integer vectors This patch implements all of those uses. llvm-svn: 283190
39 lines
1.1 KiB
LLVM
39 lines
1.1 KiB
LLVM
; RUN: llc -verify-machineinstrs < %s -mcpu=pwr7 -mattr=+vsx | FileCheck %s
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; RUN: llc -verify-machineinstrs < %s -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 | \
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; RUN: FileCheck -check-prefix=CHECK-FISL %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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declare <2 x double> @sv(<2 x double>, <2 x i64>, <4 x float>) #0
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define <2 x double> @main(<4 x float> %a, <2 x double> %b, <2 x i64> %c) #1 {
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entry:
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%ca = tail call <2 x double> @sv(<2 x double> %b, <2 x i64> %c, <4 x float> %a)
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%v = fadd <2 x double> %ca, <double 1.0, double 1.0>
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ret <2 x double> %v
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; CHECK-LABEL: @main
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; CHECK-DAG: vor [[V:[0-9]+]], 2, 2
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; CHECK-DAG: vor 2, 3, 3
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; CHECK-DAG: vor 3, 4, 4
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; CHECK-DAG: vor 4, [[V]], [[V]]
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; CHECK: bl sv
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; CHECK: lxvd2x [[VC:[0-9]+]],
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; CHECK: xvadddp 34, 34, [[VC]]
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; CHECK: blr
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; CHECK-FISL-LABEL: @main
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; CHECK-FISL: stxvd2x 34
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; CHECK-FISL: vor 2, 3, 3
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; CHECK-FISL: vor 3, 4, 4
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; CHECK-FISL: lxvd2x 36
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; CHECK-FISL: bl sv
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; CHECK-FISL: lxvd2x [[VC:[0-9]+]],
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; CHECK-FISL: xvadddp 34, 34, [[VC]]
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; CHECK-FISL: blr
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}
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attributes #0 = { noinline nounwind readnone }
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attributes #1 = { nounwind }
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