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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-19 19:12:56 +02:00
llvm-mirror/include/llvm/Target/GlobalISel
Aditya Nandakumar 1dea0652da Revert "Revert rr340111 "[GISel]: Add Legalization/lowering code for bit counting operations""
This reverts commit d1341152d91398e9a882ba2ee924147ea2f9b589.

This patch originally made use of Nested MachineIRBuilder buildInstr
calls, and since order of argument processing is not well defined, the
instructions were built slightly in a different order (still correct).
I've removed the nested buildInstr calls to have a defined order now.

Patch was tested by Mikael.

llvm-svn: 340309
2018-08-21 17:30:31 +00:00
..
RegisterBank.td Re-commit: [globalisel] Tablegen-erate current Register Bank Information 2017-01-19 11:15:55 +00:00
SelectionDAGCompat.td Revert "Revert rr340111 "[GISel]: Add Legalization/lowering code for bit counting operations"" 2018-08-21 17:30:31 +00:00
Target.td [GlobalISel][TableGen] Add support for SDNodeXForm 2018-01-16 18:44:05 +00:00