mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-02-01 05:01:59 +01:00
d654e7d40c
Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
64 lines
1.8 KiB
LLVM
64 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
|
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
|
|
|
|
define i32 @negate_nuw(i32 %x) {
|
|
; CHECK-LABEL: negate_nuw:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: xorl %eax, %eax
|
|
; CHECK-NEXT: retq
|
|
%neg = sub nuw i32 0, %x
|
|
ret i32 %neg
|
|
}
|
|
|
|
define <4 x i32> @negate_nuw_vec(<4 x i32> %x) {
|
|
; CHECK-LABEL: negate_nuw_vec:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: xorps %xmm0, %xmm0
|
|
; CHECK-NEXT: retq
|
|
%neg = sub nuw <4 x i32> zeroinitializer, %x
|
|
ret <4 x i32> %neg
|
|
}
|
|
|
|
define i8 @negate_zero_or_minsigned_nsw(i8 %x) {
|
|
; CHECK-LABEL: negate_zero_or_minsigned_nsw:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: xorl %eax, %eax
|
|
; CHECK-NEXT: retq
|
|
%signbit = and i8 %x, 128
|
|
%neg = sub nsw i8 0, %signbit
|
|
ret i8 %neg
|
|
}
|
|
|
|
define <4 x i32> @negate_zero_or_minsigned_nsw_vec(<4 x i32> %x) {
|
|
; CHECK-LABEL: negate_zero_or_minsigned_nsw_vec:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: xorps %xmm0, %xmm0
|
|
; CHECK-NEXT: retq
|
|
%signbit = shl <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
|
|
%neg = sub nsw <4 x i32> zeroinitializer, %signbit
|
|
ret <4 x i32> %neg
|
|
}
|
|
|
|
define i8 @negate_zero_or_minsigned(i8 %x) {
|
|
; CHECK-LABEL: negate_zero_or_minsigned:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: movl %edi, %eax
|
|
; CHECK-NEXT: shlb $7, %al
|
|
; CHECK-NEXT: # kill: def $al killed $al killed $eax
|
|
; CHECK-NEXT: retq
|
|
%signbit = shl i8 %x, 7
|
|
%neg = sub i8 0, %signbit
|
|
ret i8 %neg
|
|
}
|
|
|
|
define <4 x i32> @negate_zero_or_minsigned_vec(<4 x i32> %x) {
|
|
; CHECK-LABEL: negate_zero_or_minsigned_vec:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
|
|
; CHECK-NEXT: retq
|
|
%signbit = and <4 x i32> %x, <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>
|
|
%neg = sub <4 x i32> zeroinitializer, %signbit
|
|
ret <4 x i32> %neg
|
|
}
|
|
|