Bradley Smith c5c6cabc6d [ARM64] SXTW/UXTW are only valid aliases for 32-bit operations. ... llvm-svn: 205890		2014-04-09 14:44:22 +00:00
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AArch64	[AArch64 NEON]Fix a assertion failure when disassemble SHLL instruction.	2013-11-29 01:29:16 +00:00
ARM	ARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructions	2014-01-12 04:36:01 +00:00
ARM64	[ARM64] SXTW/UXTW are only valid aliases for 32-bit operations.	2014-04-09 14:44:22 +00:00
Mips	This patch implements jalx instruction for Mips architecture.This instruction executes a procedure call within the current 256 MB-aligned region and change the ISA Mode from MIPS32 to microMIPS32 or MIPS16e. Usage samples for assembler and dissasembler are provided as well.	2014-03-03 13:12:59 +00:00
PowerPC	[PowerPC] Initial support for the VSX instruction set	2014-03-13 07:58:58 +00:00
Sparc	[Sparc] Add support for decoding 'swap' instruction.	2014-03-09 23:32:07 +00:00
SystemZ	[SystemZ] Add support for z196 float<->unsigned conversions	2014-03-21 10:56:30 +00:00
X86	Test case for r204305.	2014-03-20 06:45:10 +00:00
XCore	[tests] Cleanup initialization of test suffixes.	2013-08-16 00:37:11 +00:00