Yvan Roux ff2ede76d2 [ARM] Add support for unpredictable MVN instructions. ... This fixes bugzilla 33011 https://bugs.llvm.org/show_bug.cgi?id=33011 Defines bits {19-16} as zero or unpredictable as specified by the ARM ARM in sections A8.8.116 and A8.8.117. It fixes also the usage of PC register as destination register for MVN register-shifted register version as specified in A8.8.117. Differential Revision: https://reviews.llvm.org/D41905 llvm-svn: 323954		2018-02-01 12:06:57 +00:00
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AArch64	[AArch64][SVE] Asm: PTRUE and PTRUES instructions	2018-01-22 15:29:19 +00:00
AMDGPU	[AMDGPU][MC] Corrected parsing of image opcode modifiers r128 and d16	2018-01-29 14:20:42 +00:00
ARM	[ARM] Add support for unpredictable MVN instructions.	2018-02-01 12:06:57 +00:00
AsmParser	Add triples or specify REQUIRES: default_triple to some tests	2018-01-27 23:31:09 +00:00
AVR	[AVR] Implement some missing code paths	2017-12-11 11:01:27 +00:00
BPF	bpf: print backward branch target properly	2017-11-16 19:15:36 +00:00
COFF	[CodeView] Add line numbers for inlined call sites	2018-01-18 22:55:43 +00:00
Disassembler	[ARM] Add support for unpredictable MVN instructions.	2018-02-01 12:06:57 +00:00
ELF	[MC] Fix assembler infinite loop on EH table using LEB padding.	2018-02-01 00:25:19 +00:00
Hexagon	[Hexagon] Add support for Hexagon V65	2017-12-11 18:57:54 +00:00
Lanai
MachO	[X86] Emit 11-byte or 15-byte NOPs on recent AMD targets, else default to 10-byte NOPs (PR22965)	2018-01-29 21:24:31 +00:00
Markup
Mips	[mips] Properly select abs and sqrt instructions	2018-01-23 10:09:39 +00:00
PowerPC	[PowerPC, AsmParser] Enable the mnemonic spell corrector	2017-12-16 02:42:18 +00:00
RISCV	[RISCV] Encode RISCV specific ELF e_flags to RISCV Binary by RISCVTargetStreamer	2018-01-26 07:53:07 +00:00
Sparc
SystemZ
WebAssembly	[WebAssembly] MC: Resolve aliases when creating provisional table entries	2018-01-31 19:28:47 +00:00
X86	[X86] Emit 11-byte or 15-byte NOPs on recent AMD targets, else default to 10-byte NOPs (PR22965)	2018-01-29 21:24:31 +00:00