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f7ea499702
Part of the effort to refactoring frame pointer code generation. We used to use two function attributes "no-frame-pointer-elim" and "no-frame-pointer-elim-non-leaf" to represent three kinds of frame pointer usage: (all) frames use frame pointer, (non-leaf) frames use frame pointer, (none) frame use frame pointer. This CL makes the idea explicit by using only one enum function attribute "frame-pointer" Option "-frame-pointer=" replaces "-disable-fp-elim" for tools such as llc. "no-frame-pointer-elim" and "no-frame-pointer-elim-non-leaf" are still supported for easy migration to "frame-pointer". tests are mostly updated with // replace command line args ‘-disable-fp-elim=false’ with ‘-frame-pointer=none’ grep -iIrnl '\-disable-fp-elim=false' * | xargs sed -i '' -e "s/-disable-fp-elim=false/-frame-pointer=none/g" // replace command line args ‘-disable-fp-elim’ with ‘-frame-pointer=all’ grep -iIrnl '\-disable-fp-elim' * | xargs sed -i '' -e "s/-disable-fp-elim/-frame-pointer=all/g" Patch by Yuanfang Chen (tabloid.adroit)! Differential Revision: https://reviews.llvm.org/D56351 llvm-svn: 351049
53 lines
2.2 KiB
LLVM
53 lines
2.2 KiB
LLVM
; RUN: llc < %s -relocation-model=pic -frame-pointer=all -mcpu=cortex-a8 -pre-RA-sched=source -no-integrated-as | FileCheck %s
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target triple = "thumbv7-apple-ios"
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; <rdar://problem/10032939>
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;
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; The vector %v2 is built like this:
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;
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; %6:ssub_1 = ...
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; %6:ssub_0 = VLDRS %const.0, 0, 14, %noreg; mem:LD4[ConstantPool] DPR_VFP2:%6
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;
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; When %6 spills, the VLDRS constant pool load cannot be rematerialized
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; since it implicitly reads the ssub_1 sub-register.
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;
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; CHECK: f1
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; CHECK: vmov d0, r0, r0
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; CHECK: vldr s1, LCPI
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; The vector must be spilled:
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; CHECK: vstr d0,
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; CHECK: asm clobber d0
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; And reloaded after the asm:
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; CHECK: vldr [[D16:d[0-9]+]],
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; CHECK: vstr [[D16]], [r1]
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define void @f1(float %x, <2 x float>* %p) {
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%v1 = insertelement <2 x float> undef, float %x, i32 0
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%v2 = insertelement <2 x float> %v1, float 0x400921FB60000000, i32 1
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%y = call double asm sideeffect "asm clobber $0", "=w,0,~{d1},~{d2},~{d3},~{d4},~{d5},~{d6},~{d7},~{d8},~{d9},~{d10},~{d11},~{d12},~{d13},~{d14},~{d15},~{d16},~{d17},~{d18},~{d19},~{d20},~{d21},~{d22},~{d23},~{d24},~{d25},~{d26},~{d27},~{d28},~{d29},~{d30},~{d31}"(<2 x float> %v2) nounwind
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store <2 x float> %v2, <2 x float>* %p, align 8
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ret void
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}
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; On the other hand, when the partial redef doesn't read the full register
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; because the bits are undef, we should rematerialize. The vector is now built
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; like this:
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;
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; %2:ssub_0 = VLDRS %const.0, 0, 14, %noreg, implicit-def %2; mem:LD4[ConstantPool]
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;
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; The extra <imp-def> operand indicates that the instruction fully defines the
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; virtual register. It doesn't read the old value.
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;
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; CHECK: f2
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; CHECK: vldr s0, LCPI
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; The vector must not be spilled:
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; CHECK-NOT: vstr
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; CHECK: asm clobber d0
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; But instead rematerialize after the asm:
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; CHECK: vldr [[S0:s[0-9]+]], LCPI
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; CHECK: vstr [[D0:d[0-9]+]], [r0]
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define void @f2(<2 x float>* %p) {
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%v2 = insertelement <2 x float> undef, float 0x400921FB60000000, i32 0
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%y = call double asm sideeffect "asm clobber $0", "=w,0,~{d1},~{d2},~{d3},~{d4},~{d5},~{d6},~{d7},~{d8},~{d9},~{d10},~{d11},~{d12},~{d13},~{d14},~{d15},~{d16},~{d17},~{d18},~{d19},~{d20},~{d21},~{d22},~{d23},~{d24},~{d25},~{d26},~{d27},~{d28},~{d29},~{d30},~{d31}"(<2 x float> %v2) nounwind
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store <2 x float> %v2, <2 x float>* %p, align 8
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ret void
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}
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