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312bcfdb97
Summary: This patch handles assembly and disassembly, but not codegen, as of yet. Additionally, it fixes a bug whereby SP and PC as shifted-reg operands were treated as predictable in ARMv7 Thumb; and it enables the tests for invalid and unpredictable instructions to run on both ARMv7 and ARMv8. Reviewers: jmolloy, rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D14141 llvm-svn: 251516
37 lines
617 B
Plaintext
37 lines
617 B
Plaintext
# RUN: llvm-mc -disassemble -triple thumbv8 -mattr=+db -show-encoding 2>%t < %s | FileCheck %s
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# RUN: FileCheck -allow-empty -check-prefix=STDERR < %t %s
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0x80 0xba
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# CHECK: hlt #0
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0xbf 0xba
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# CHECK: hlt #63
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# DCPS{1,2,3}
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0x8f 0xf7 0x01 0x80
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# CHECK: dcps1
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0x8f 0xf7 0x02 0x80
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# CHECK: dcps2
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0x8f 0xf7 0x03 0x80
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# CHECK: dcps3
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0xbf 0xf3 0x59 0x8f
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0xbf 0xf3 0x51 0x8f
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0xbf 0xf3 0x55 0x8f
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0xbf 0xf3 0x5d 0x8f
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# CHECK: dmb ishld
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# CHECK: dmb oshld
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# CHECK: dmb nshld
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# CHECK: dmb ld
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[0x00 0xf0 0x00 0x0d]
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[0x63 0xeb 0x2d 0x46]
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# CHECK: and sp, r0, #0
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# CHECK: sbc.w r6, r3, sp, asr #16
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# STDERR-NOT: warning
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