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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 11:13:28 +01:00
llvm-mirror/test/CodeGen
Konstantin Pyzhov 8ae1180dde [AMDGPU] Corrected declaration of VOPC instructions with SDWA addressing mode.
Removed "implicit def VCC" from declarations of AMDGPU VOPC instructions since they do not implicitly write to VCC in SDWA mode.

Differential Revision: https://reviews.llvm.org/D89168
2020-11-05 11:15:50 -05:00
..
AArch64 [AArch64][GlobalISel] Add AArch64::G_DUPLANE[X] opcodes for lane duplicates. 2020-11-05 11:18:11 -08:00
AMDGPU [AMDGPU] Corrected declaration of VOPC instructions with SDWA addressing mode. 2020-11-05 11:15:50 -05:00
ARC
ARM [MachineOutliner] Do not outline debug instructions 2020-11-05 19:26:51 +00:00
AVR
BPF [NewPM] Provide method to run all pipeline callbacks, used for -O0 2020-11-04 22:27:16 -08:00
Generic
Hexagon
Inputs
Lanai
Mips
MIR
MSP430
NVPTX
PowerPC [MachineSink] add more profitable pattern. 2020-11-04 23:11:22 -05:00
RISCV [RISCV] Add isel patterns for fnmadd/fnmsub with an fneg on the second operand instead of the first. 2020-11-05 14:00:25 -08:00
SPARC
SystemZ
Thumb
Thumb2 [ARM] Make tests less dependent on scheduling. NFC 2020-11-05 08:26:55 +00:00
VE [VE] Add isReMaterializable and isAsCheapAsAMove flags 2020-11-06 06:09:10 +09:00
WebAssembly
WinCFGuard
WinEH
X86 [MachineSink] add more profitable pattern. 2020-11-04 23:11:22 -05:00
XCore