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https://github.com/RPCS3/llvm-mirror.git
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b434098ac8
SUMMARY: 1. in the patch , remove setting storageclass in function .getXCOFFSection and construct function of class MCSectionXCOFF there are XCOFF::StorageMappingClass MappingClass; XCOFF::SymbolType Type; XCOFF::StorageClass StorageClass; in the MCSectionXCOFF class, these attribute only used in the XCOFFObjectWriter, (asm path do not need the StorageClass) we need get the value of StorageClass, Type,MappingClass before we invoke the getXCOFFSection every time. actually , we can get the StorageClass of the MCSectionXCOFF from it's delegated symbol. 2. we also change the oprand of branch instruction from symbol name to qualify symbol name. for example change bl .foo extern .foo to bl .foo[PR] extern .foo[PR] 3. and if there is reference indirect call a function bar. we also add extern .bar[PR] Reviewers: Jason liu, Xiangling Liao Differential Revision: https://reviews.llvm.org/D84765
99 lines
3.3 KiB
LLVM
99 lines
3.3 KiB
LLVM
; RUN: llc -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 -mattr=-altivec \
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; RUN: -stop-after=machine-cp --verify-machineinstrs < %s | FileCheck \
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; RUN: --check-prefixes=MIR,MIR32 %s
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; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr4 -mattr=-altivec \
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; RUN: -stop-after=machine-cp --verify-machineinstrs < %s | FileCheck \
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; RUN: --check-prefixes=MIR,MIR64 %s
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; RUN: llc -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 -mattr=-altivec \
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; RUN: --verify-machineinstrs < %s | FileCheck --check-prefixes=ASM,ASM32 %s
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; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr4 -mattr=-altivec \
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; RUN: --verify-machineinstrs < %s | FileCheck --check-prefixes=ASM,ASM64 %s
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%struct.S = type { i8 }
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%struct.T = type { double, i32, i32, i32, float }
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define void @test1() {
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entry:
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%s = alloca %struct.S, align 4
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call void @foo(%struct.S* sret %s)
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ret void
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}
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define void @test2() {
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entry:
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%t = alloca %struct.T, align 8
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call void @bar(%struct.T* sret %t)
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ret void
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}
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declare void @foo(%struct.S* sret)
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declare void @bar(%struct.T* sret)
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; MIR: name: test1
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; MIR: stack:
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; MIR-NEXT: - { id: 0, name: s, type: default, offset: 0, size: 1, alignment: 8,
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; MIR32: bb.0.entry:
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; MIR32-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
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; MIR32-NEXT: renamable $r3 = ADDI %stack.0.s, 0
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; MIR32-NEXT: BL_NOP <mcsymbol .foo[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1
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; MIR32-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
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; MIR64: bb.0.entry:
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; MIR64-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
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; MIR64-NEXT: renamable $x3 = ADDI8 %stack.0.s, 0
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; MIR64-NEXT: BL8_NOP <mcsymbol .foo[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
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; MIR64-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
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; ASM-LABEL: .test1:
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; ASM32: stwu 1, -64(1)
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; ASM32-NEXT: addi 3, 1, 56
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; ASM32-NEXT: bl .foo[PR]
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; ASM32-NEXT: nop
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; ASM32-NEXT: addi 1, 1, 64
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; ASM64: stdu 1, -128(1)
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; ASM64-NEXT: addi 3, 1, 120
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; ASM64-NEXT: bl .foo[PR]
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; ASM64-NEXT: nop
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; ASM64-NEXT: addi 1, 1, 128
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; MIR: name: test2
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; MIR: stack:
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; MIR-NEXT: - { id: 0, name: t, type: default, offset: 0, size: 24, alignment: 8,
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; MIR32: bb.0.entry:
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; MIR32-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
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; MIR32-NEXT: renamable $r3 = ADDI %stack.0.t, 0
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; MIR32-NEXT: BL_NOP <mcsymbol .bar[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1
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; MIR32-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
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; MIR64: bb.0.entry:
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; MIR64-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
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; MIR64-NEXT: renamable $x3 = ADDI8 %stack.0.t, 0
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; MIR64-NEXT: BL8_NOP <mcsymbol .bar[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
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; MIR64-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
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; ASM-LABEL: .test2:
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; ASM32: stwu 1, -80(1)
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; ASM32-NEXT: addi 3, 1, 56
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; ASM32-NEXT: bl .bar[PR]
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; ASM32-NEXT: nop
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; ASM32-NEXT: addi 1, 1, 80
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; ASM64: stdu 1, -144(1)
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; ASM64-NEXT: addi 3, 1, 120
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; ASM64-NEXT: bl .bar[PR]
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; ASM64-NEXT: nop
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; ASM64-NEXT: addi 1, 1, 144
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