mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 19:23:23 +01:00
d49cb60862
Summary: This catches malformed mir files which specify alignment as log2 instead of pow2. See https://reviews.llvm.org/D65945 for reference, This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67433 llvm-svn: 371608
58 lines
1.4 KiB
YAML
58 lines
1.4 KiB
YAML
# This file tests the scenario when ISEL is the last instruction of the last
|
|
# Basic Block, i.e., the BB cannot fall through to its successor situation.
|
|
# RUN: llc -ppc-gen-isel=false -run-pass ppc-expand-isel -o - %s | FileCheck %s
|
|
|
|
--- |
|
|
target datalayout = "E-m:e-i64:64-n32:64"
|
|
target triple = "powerpc64-unknown-linux-gnu"
|
|
define signext i32 @testExpandISEL(i32 signext %i, i32 signext %j) {
|
|
entry:
|
|
%cmp = icmp sgt i32 %i, 0
|
|
%add = add nsw i32 %i, 1
|
|
%cond = select i1 %cmp, i32 %add, i32 %j
|
|
ret i32 %cond
|
|
}
|
|
|
|
...
|
|
---
|
|
name: testExpandISEL
|
|
alignment: 4
|
|
exposesReturnsTwice: false
|
|
legalized: false
|
|
regBankSelected: false
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
liveins:
|
|
- { reg: '$x0' }
|
|
- { reg: '$x3' }
|
|
frameInfo:
|
|
isFrameAddressTaken: false
|
|
isReturnAddressTaken: false
|
|
hasStackMap: false
|
|
hasPatchPoint: false
|
|
stackSize: 0
|
|
offsetAdjustment: 0
|
|
maxAlignment: 0
|
|
adjustsStack: false
|
|
hasCalls: false
|
|
maxCallFrameSize: 0
|
|
hasOpaqueSPAdjustment: false
|
|
hasVAStart: false
|
|
hasMustTailInVarArgFunc: false
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $x0, $x3
|
|
|
|
$r5 = ADDI $r3, 1
|
|
$cr0 = CMPWI $r3, 0
|
|
$r3 = ISEL $zero, $r0, $cr0gt
|
|
; CHECK: BC $cr0gt, %[[TRUE:bb.[0-9]+]]
|
|
; CHECK: %[[FALSE:bb.[0-9]+]]
|
|
; CHECK: $r3 = ORI $r0, 0
|
|
; CHECK: B %[[SUCCESSOR:bb.[0-9]+]]
|
|
; CHECK: [[TRUE]]
|
|
; CHECK: $r3 = ADDI $zero, 0
|
|
|
|
|
|
...
|