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a3d207d6bc
This reverts commit bf544fa1c3cb80f24d85e84559fb11193846259f. Fixed the typo in PPCInstrInfo.cpp.
99 lines
3.6 KiB
LLVM
99 lines
3.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck %s
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; The purpose of this test is to check the call protocols for the situation
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; where the caller has PC Relative disabled, the callee has PC Relative
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; enabled and both functions are in the same file.
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; Note that the callee does not know if it clobbers the TOC because it
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; contains an external call to @externalFunc.
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@global = external local_unnamed_addr global i32, align 4
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define dso_local signext i32 @callee(i32 signext %a) local_unnamed_addr #0 {
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; CHECK-LABEL: callee:
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; CHECK: .localentry callee, 1
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; CHECK-NEXT: # %bb.0: # %entry
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
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; CHECK-NEXT: std r0, 16(r1)
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; CHECK-NEXT: stdu r1, -48(r1)
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; CHECK-NEXT: mr r30, r3
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; CHECK-NEXT: bl externalFunc@notoc
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; CHECK-NEXT: add r3, r3, r30
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; CHECK-NEXT: extsw r3, r3
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; CHECK-NEXT: addi r1, r1, 48
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; CHECK-NEXT: ld r0, 16(r1)
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; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
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; CHECK-NEXT: mtlr r0
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; CHECK-NEXT: blr
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entry:
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%call = tail call signext i32 @externalFunc(i32 signext %a) #3
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%add = add nsw i32 %call, %a
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ret i32 %add
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}
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declare signext i32 @externalFunc(i32 signext) local_unnamed_addr #1
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define dso_local void @caller(i32 signext %a) local_unnamed_addr #2 {
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; CHECK-LABEL: caller:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
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; CHECK-NEXT: std r0, 16(r1)
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; CHECK-NEXT: stdu r1, -48(r1)
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; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
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; CHECK-NEXT: ld r30, .LC0@toc@l(r4)
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; CHECK-NEXT: lwz r4, 0(r30)
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; CHECK-NEXT: add r3, r4, r3
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; CHECK-NEXT: extsw r3, r3
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; CHECK-NEXT: bl callee
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; CHECK-NEXT: nop
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; CHECK-NEXT: mullw r3, r3, r3
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; CHECK-NEXT: stw r3, 0(r30)
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; CHECK-NEXT: addi r1, r1, 48
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; CHECK-NEXT: ld r0, 16(r1)
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; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
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; CHECK-NEXT: mtlr r0
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; CHECK-NEXT: blr
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entry:
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%0 = load i32, i32* @global, align 4
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%add = add nsw i32 %0, %a
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%call = tail call signext i32 @callee(i32 signext %add)
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%mul = mul nsw i32 %call, %call
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store i32 %mul, i32* @global, align 4
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ret void
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}
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define dso_local signext i32 @tail_caller(i32 signext %a) local_unnamed_addr #2 {
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; CHECK-LABEL: tail_caller:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: std r0, 16(r1)
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; CHECK-NEXT: stdu r1, -32(r1)
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; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
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; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
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; CHECK-NEXT: lwz r4, 0(r4)
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; CHECK-NEXT: add r3, r4, r3
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; CHECK-NEXT: extsw r3, r3
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; CHECK-NEXT: bl callee
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; CHECK-NEXT: nop
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; CHECK-NEXT: addi r1, r1, 32
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; CHECK-NEXT: ld r0, 16(r1)
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; CHECK-NEXT: mtlr r0
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; CHECK-NEXT: blr
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entry:
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%0 = load i32, i32* @global, align 4
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%add = add nsw i32 %0, %a
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%call = tail call signext i32 @callee(i32 signext %add)
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ret i32 %call
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}
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; Left the target features in this test because it is important that caller has
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; -pcrelative-memops while callee has +pcrelative-memops
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attributes #0 = { nounwind "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+pcrelative-memops,+power8-vector,+power9-vector,+vsx,-htm,-spe" }
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attributes #1 = { "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+pcrelative-memops,+power8-vector,+power9-vector,+vsx,-htm,-spe" }
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attributes #2 = { nounwind "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+power9-vector,+vsx,-htm,-pcrelative-memops,-spe" }
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attributes #3 = { nounwind }
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