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3f23d4b8c3
tryLatency compares two sched candidates. For the top zone it prefers the one with lesser depth, but only if that depth is greater than the total latency of the instructions we've already scheduled -- otherwise its latency would be hidden and there would be no stall. Unfortunately it only tests the depth of one of the candidates. This can lead to situations where the TopDepthReduce heuristic does not kick in, but a lower priority heuristic chooses the other candidate, whose depth *is* greater than the already scheduled latency, which causes a stall. The fix is to apply the heuristic if the depth of *either* candidate is greater than the already scheduled latency. All this also applies to the BotHeightReduce heuristic in the bottom zone. Differential Revision: https://reviews.llvm.org/D72392
52 lines
1.5 KiB
LLVM
52 lines
1.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mcpu=pwr9 -O3 < %s | FileCheck %s -check-prefix=PPC64LE
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target datalayout = "e-m:e-i64:64-n32:64"
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target triple = "powerpc64le-unknown-linux-gnu"
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@global.6 = external global i32*
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declare void @barney.88(i1, i32*)
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declare void @barney.94(i8*, i32)
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define void @redundancy_on_ppc_only(i1 %arg7) nounwind {
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; PPC64LE-LABEL: redundancy_on_ppc_only:
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; PPC64LE: # %bb.0: # %bb
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; PPC64LE-NEXT: mflr 0
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; PPC64LE-NEXT: andi. 3, 3, 1
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; PPC64LE-NEXT: std 0, 16(1)
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; PPC64LE-NEXT: stdu 1, -32(1)
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; PPC64LE-NEXT: li 3, 1
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; PPC64LE-NEXT: li 4, 0
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; PPC64LE-NEXT: iselgt 3, 3, 4
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; PPC64LE-NEXT: bl barney.88
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; PPC64LE-NEXT: nop
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; PPC64LE-NEXT: addi 1, 1, 32
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; PPC64LE-NEXT: ld 0, 16(1)
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; PPC64LE-NEXT: mtlr 0
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; PPC64LE-NEXT: blr
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bb:
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br label %bb10
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bb10: ; preds = %bb
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call void @barney.88(i1 %arg7, i32* null)
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ret void
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}
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define void @redundancy_on_ppc_and_other_targets() nounwind {
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; PPC64LE-LABEL: redundancy_on_ppc_and_other_targets:
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; PPC64LE: # %bb.0:
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; PPC64LE-NEXT: mflr 0
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; PPC64LE-NEXT: std 0, 16(1)
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; PPC64LE-NEXT: stdu 1, -32(1)
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; PPC64LE-NEXT: addis 3, 2, .LC0@toc@ha
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; PPC64LE-NEXT: li 4, 0
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; PPC64LE-NEXT: ld 3, .LC0@toc@l(3)
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; PPC64LE-NEXT: std 4, 0(3)
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; PPC64LE-NEXT: bl barney.94
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; PPC64LE-NEXT: nop
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store i32* null, i32** @global.6
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call void @barney.94(i8* undef, i32 0)
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unreachable
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}
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