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6f49436f61
If the instruction have match pattern, llvm-tblgen will infer the sideeffect bit from the match pattern and it works well. If not, the tblgen will set it as true that hurt the scheduling. PowerPC has some instructions that didn't specify the match pattern(i.e. LXSD etc), which is manually selected post-ra according to the register pressure. We need to clear the sideeffect flag for these instructions. Differential Revision: https://reviews.llvm.org/D69232
59 lines
2.9 KiB
LLVM
59 lines
2.9 KiB
LLVM
; REQUIRES: asserts
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; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
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; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK-P9
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define i64 @store_disjoint_memory(i64* nocapture %P, i64 %v) {
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entry:
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; CHECK: ********** MI Scheduling **********
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; CHECK-LABEL: store_disjoint_memory:%bb.0
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; CHECK:SU([[REG2:[0-9]+]]): STD renamable $x{{[0-9]+}}, 24, renamable $x[[REG5:[0-9]+]]
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; CHECK-NOT: Successors:
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; CHECK-NOT: SU([[REG3]]): Ord Latency=0 Memory
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; CHECK:SU([[REG3:[0-9]+]]): STD renamable $x{{[0-9]+}}, 16, renamable $x[[REG5]]
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; CHECK: Predecessors:
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; CHECK-NOT: SU([[REG2]]): Ord Latency=0 Memory
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%arrayidx = getelementptr inbounds i64, i64* %P, i64 3
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store i64 %v, i64* %arrayidx
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%arrayidx1 = getelementptr inbounds i64, i64* %P, i64 2
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store i64 %v, i64* %arrayidx1
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ret i64 %v
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}
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; LXSD is an instruction that can be modeled.
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@gd = external local_unnamed_addr global [500 x double], align 8
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@gf = external local_unnamed_addr global [500 x float], align 4
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define double @test_lxsd_no_barrier(double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, double %i, double %j, double %k, double %l, double %m) {
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entry:
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%0 = load double, double* getelementptr inbounds ([500 x double], [500 x double]* @gd, i64 0, i64 10), align 8
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%1 = load double, double* getelementptr inbounds ([500 x double], [500 x double]* @gd, i64 0, i64 17), align 8
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%2 = load double, double* getelementptr inbounds ([500 x double], [500 x double]* @gd, i64 0, i64 87), align 8
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%3 = load double, double* getelementptr inbounds ([500 x double], [500 x double]* @gd, i64 0, i64 97), align 8
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%4 = load double, double* getelementptr inbounds ([500 x double], [500 x double]* @gd, i64 0, i64 77), align 8
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%add = fadd double %a, %b
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%add1 = fadd double %add, %c
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%add2 = fadd double %add1, %d
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%add3 = fadd double %add2, %e
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%add4 = fadd double %add3, %f
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%add5 = fadd double %add4, %g
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%add6 = fadd double %add5, %h
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%add7 = fadd double %add6, %i
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%add8 = fadd double %add7, %j
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%add9 = fadd double %add8, %k
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%add10 = fadd double %add9, %l
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%add11 = fadd double %add10, %m
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%add12 = fadd double %add11, %0
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%add13 = fadd double %add12, %1
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%add14 = fadd double %add13, %2
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%add15 = fadd double %add14, %3
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%add16 = fadd double %add15, %4
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ret double %add16
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; CHECK-P9: ********** MI Scheduling **********
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; CHECK-P9-LABEL: test_lxsd_no_barrier:%bb.0 entry
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; CHECK-P9-NOT:Global memory object and new barrier chain: SU({{[0-9]+}}).
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; CHECK-P9:SU({{[0-9]+}}): renamable $vf{{[0-9]+}} = LXSD 136
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; CHECK-P9:SU({{[0-9]+}}): renamable $vf{{[0-9]+}} = LXSD 696
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; CHECK-P9:SU({{[0-9]+}}): renamable $vf{{[0-9]+}} = LXSD 776
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; CHECK-P9:SU({{[0-9]+}}): renamable $vf{{[0-9]+}} = LXSD 616
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}
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