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2f3956c41c
When switched to the MI scheduler for P9, the hardware is modeled as out of order. However, inside the MI Scheduler algorithm, we still use the in-order scheduling model as the MicroOpBufferSize isn't set. The MI scheduler take it as the hw cannot buffer the op. So, only when all the available instructions issued, the pending instruction could be scheduled. That is not true for our P9 hw in fact. This patch is trying to enable the Out-of-Order scheduling model. The buffer size 44 is picked from the P9 hw spec, and the perf test indicate that, its value won't hurt the cpu2017. With this patch, there are 3 specs improved over 3% and 1 spec deg over 3%. The detail is as follows: x264_r: +6.95% cactuBSSN_r: +6.94% lbm_r: +4.11% xz_r: -3.85% And the GEOMEAN for all the C/C++ spec in spec2017 is about 0.18% improved. Reviewer: Nemanjai Differential Revision: https://reviews.llvm.org/D55810 llvm-svn: 350285
108 lines
3.9 KiB
LLVM
108 lines
3.9 KiB
LLVM
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx \
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; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx \
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; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck \
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; RUN: -check-prefix=CHECK-REG %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 \
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; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 \
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; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | \
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; RUN: FileCheck -check-prefix=CHECK-FISL %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr \
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; RUN: -ppc-asm-full-reg-names < %s | FileCheck -check-prefix=CHECK-P9-REG %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -fast-isel -O0 \
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; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck \
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; RUN: -check-prefix=CHECK-P9-FISL %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define double @foo1(double %a) nounwind {
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entry:
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call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() nounwind
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br label %return
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; CHECK-REG: @foo1
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; CHECK-REG: xxlor v2, f1, f1
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; CHECK-REG: xxlor f1, v2, v2
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; CHECK-REG: blr
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; CHECK-FISL: @foo1
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; CHECK-FISL-NOT: lis
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; CHECK-FISL-NOT: ori
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; CHECK-FISL: li r3, -152
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; CHECK-FISL-NOT: lis
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; CHECK-FISL-NOT: ori
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; CHECK-FISL: stxsdx f1, r1, r3
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; CHECK-FISL: blr
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; CHECK-P9-REG: @foo1
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; CHECK-P9-REG: xscpsgndp v2, f1, f1
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; CHECK-P9-REG: xscpsgndp f1, v2, v2
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; CHECK-P9-REG: blr
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; CHECK-P9-FISL: @foo1
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; CHECK-P9-FISL: stfd f31, -8(r1)
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; CHECK-P9-FISL: blr
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return: ; preds = %entry
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ret double %a
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}
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define double @foo2(double %a) nounwind {
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entry:
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%b = fadd double %a, %a
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call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() nounwind
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br label %return
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; CHECK-REG: @foo2
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; CHECK-REG: {{xxlor|xsadddp}} v2, f1, f1
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; CHECK-REG: {{xxlor|xsadddp}} f1, f0, f0
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; CHECK-REG: blr
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; CHECK-FISL: @foo2
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; CHECK-FISL: xsadddp [[REG0:f[0-9]+]], f1, f1
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; CHECK-FISL: stxsdx [[REG0]], r1, r3
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; CHECK-FISL: lxsdx f1, r1, r3
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; CHECK-FISL: blr
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; CHECK-P9-REG: @foo2
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; CHECK-P9-REG: {{xscpsgndp|xsadddp}} v2, f1, f1
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; CHECK-P9-REG: {{xscpsgndp|xsadddp}} f1, v2, v2
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; CHECK-P9-REG: blr
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; CHECK-P9-FISL: @foo2
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; CHECK-P9-FISL: xsadddp [[REG0:f[0-9]+]], f1, f1
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; CHECK-P9-FISL: stfd [[REG0]], -152(r1)
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; CHECK-P9-FISL: lfd f1, -152(r1)
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; CHECK-P9-FISL: blr
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return: ; preds = %entry
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ret double %b
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}
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define double @foo3(double %a) nounwind {
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entry:
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call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31},~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"() nounwind
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br label %return
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; CHECK: @foo3
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; CHECK: stxsdx f1, r1, r3
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; CHECK: lxsdx f0, r1, r3
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; CHECK: xsadddp f1, f0, f0
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; CHECK: blr
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; CHECK-P9-REG-LABEL: foo3
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; CHECK-P9-REG: stdu r1, -400(r1)
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; CHECK-P9-REG-DAG: lfd f30, 384(r1)
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; CHECK-P9-REG-DAG: xsadddp f1, f0, f0
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; CHECK-P9-FISL-LABEL: foo3
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; CHECK-P9-FISL: stdu r1, -400(r1)
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; CHECK-P9-FISL: lfd f0, 56(r1)
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; CHECK-P9-FISL: xsadddp f1, f0, f0
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return: ; preds = %entry
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%b = fadd double %a, %a
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ret double %b
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}
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