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https://github.com/RPCS3/llvm-mirror.git
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9e9fc74a34
The instruction makes use of a previously ignored field in the fence instruction. It is introduced in the version 2.3 draft of the RISC-V specification after much work by the Memory Model Task Group. As clarified here <https://github.com/riscv/riscv-isa-manual/issues/186>, the fence.tso assembler mnemonic does not have operands. llvm-svn: 334278
244 lines
6.8 KiB
ArmAsm
244 lines
6.8 KiB
ArmAsm
# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
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# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
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# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
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# RUN: | llvm-objdump -riscv-no-aliases -d - \
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# RUN: | FileCheck -check-prefix=CHECK-INST %s
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# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
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# RUN: | llvm-objdump -riscv-no-aliases -d - \
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# RUN: | FileCheck -check-prefix=CHECK-INST %s
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# CHECK-INST: lui a0, 2
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# CHECK: encoding: [0x37,0x25,0x00,0x00]
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lui a0, 2
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# CHECK-INST: lui s11, 552960
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# CHECK: encoding: [0xb7,0x0d,0x00,0x87]
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lui s11, (0x87000000>>12)
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# CHECK-INST: lui a0, 0
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# CHECK: encoding: [0x37,0x05,0x00,0x00]
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lui a0, %hi(2)
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# CHECK-INST: lui s11, 552960
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# CHECK: encoding: [0xb7,0x0d,0x00,0x87]
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lui s11, (0x87000000>>12)
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# CHECK-INST: lui s11, 552960
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# CHECK: encoding: [0xb7,0x0d,0x00,0x87]
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lui s11, %hi(0x87000000)
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# CHECK-INST: lui t0, 1048575
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# CHECK: encoding: [0xb7,0xf2,0xff,0xff]
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lui t0, 1048575
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# CHECK-INST: lui gp, 0
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# CHECK: encoding: [0xb7,0x01,0x00,0x00]
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lui gp, 0
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# CHECK-INST: auipc a0, 2
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# CHECK: encoding: [0x17,0x25,0x00,0x00]
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auipc a0, 2
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# CHECK-INST: auipc s11, 552960
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# CHECK: encoding: [0x97,0x0d,0x00,0x87]
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auipc s11, (0x87000000>>12)
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# CHECK-INST: auipc t0, 1048575
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# CHECK: encoding: [0x97,0xf2,0xff,0xff]
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auipc t0, 1048575
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# CHECK-INST: auipc gp, 0
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# CHECK: encoding: [0x97,0x01,0x00,0x00]
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auipc gp, 0
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# CHECK-INST: jal a2, 1048574
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# CHECK: encoding: [0x6f,0xf6,0xff,0x7f]
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jal a2, 1048574
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# CHECK-INST: jal a3, 256
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# CHECK: encoding: [0xef,0x06,0x00,0x10]
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jal a3, 256
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# CHECK-INST: jalr a0, a1, -2048
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# CHECK: encoding: [0x67,0x85,0x05,0x80]
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jalr a0, a1, -2048
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# CHECK-INST: jalr a0, a1, -2048
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# CHECK: encoding: [0x67,0x85,0x05,0x80]
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jalr a0, a1, %lo(2048)
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# CHECK-INST: jalr t2, t1, 2047
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# CHECK: encoding: [0xe7,0x03,0xf3,0x7f]
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jalr t2, t1, 2047
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# CHECK-INST: jalr sp, zero, 256
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# CHECK: encoding: [0x67,0x01,0x00,0x10]
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jalr sp, zero, 256
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# CHECK-INST: beq s1, s1, 102
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# CHECK: encoding: [0x63,0x83,0x94,0x06]
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beq s1, s1, 102
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# CHECK-INST: bne a4, a5, -4096
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# CHECK: encoding: [0x63,0x10,0xf7,0x80]
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bne a4, a5, -4096
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# CHECK-INST: blt sp, gp, 4094
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# CHECK: encoding: [0xe3,0x4f,0x31,0x7e]
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blt sp, gp, 4094
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# CHECK-INST: bge s2, ra, -224
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# CHECK: encoding: [0xe3,0x50,0x19,0xf2]
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bge s2, ra, -224
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# CHECK-INST: bltu zero, zero, 0
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# CHECK: encoding: [0x63,0x60,0x00,0x00]
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bltu zero, zero, 0
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# CHECK-INST: bgeu s8, sp, 512
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# CHECK: encoding: [0x63,0x70,0x2c,0x20]
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bgeu s8, sp, 512
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# CHECK-INST: lb s3, 4(ra)
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# CHECK: encoding: [0x83,0x89,0x40,0x00]
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lb s3, 4(ra)
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# CHECK-INST: lb s3, 4(ra)
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# CHECK: encoding: [0x83,0x89,0x40,0x00]
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lb s3, +4(ra)
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# CHECK-INST: lh t1, -2048(zero)
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# CHECK: encoding: [0x03,0x13,0x00,0x80]
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lh t1, -2048(zero)
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# CHECK-INST: lh t1, -2048(zero)
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# CHECK: encoding: [0x03,0x13,0x00,0x80]
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lh t1, %lo(2048)(zero)
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# CHECK-INST: lh sp, 2047(a0)
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# CHECK: encoding: [0x03,0x11,0xf5,0x7f]
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lh sp, 2047(a0)
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# CHECK-INST: lw a0, 97(a2)
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# CHECK: encoding: [0x03,0x25,0x16,0x06]
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lw a0, 97(a2)
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# CHECK-INST: lbu s5, 0(s6)
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# CHECK: encoding: [0x83,0x4a,0x0b,0x00]
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lbu s5, 0(s6)
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# CHECK-INST: lhu t3, 255(t3)
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# CHECK: encoding: [0x03,0x5e,0xfe,0x0f]
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lhu t3, 255(t3)
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# CHECK-INST: sb a0, 2047(a2)
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# CHECK: encoding: [0xa3,0x0f,0xa6,0x7e]
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sb a0, 2047(a2)
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# CHECK-INST: sh t3, -2048(t5)
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# CHECK: encoding: [0x23,0x10,0xcf,0x81]
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sh t3, -2048(t5)
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# CHECK-INST: sh t3, -2048(t5)
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# CHECK: encoding: [0x23,0x10,0xcf,0x81]
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sh t3, %lo(2048)(t5)
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# CHECK-INST: sw ra, 999(zero)
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# CHECK: encoding: [0xa3,0x23,0x10,0x3e]
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sw ra, 999(zero)
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# CHECK-INST: addi ra, sp, 2
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# CHECK: encoding: [0x93,0x00,0x21,0x00]
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addi ra, sp, 2
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# CHECK-INST: slti a0, a2, -20
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# CHECK: encoding: [0x13,0x25,0xc6,0xfe]
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slti a0, a2, -20
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# CHECK-INST: sltiu s2, s3, 80
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# CHECK: encoding: [0x13,0xb9,0x09,0x05]
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sltiu s2, s3, 0x50
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# CHECK-INST: xori tp, t1, -99
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# CHECK: encoding: [0x13,0x42,0xd3,0xf9]
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xori tp, t1, -99
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# CHECK-INST: ori a0, a1, -2048
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# CHECK: encoding: [0x13,0xe5,0x05,0x80]
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ori a0, a1, -2048
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# CHECK-INST: ori a0, a1, -2048
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# CHECK: encoding: [0x13,0xe5,0x05,0x80]
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ori a0, a1, %lo(2048)
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# CHECK-INST: andi ra, sp, 2047
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# CHECK: encoding: [0x93,0x70,0xf1,0x7f]
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andi ra, sp, 2047
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# CHECK-INST: andi ra, sp, 2047
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# CHECK: encoding: [0x93,0x70,0xf1,0x7f]
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andi x1, x2, 2047
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# CHECK-INST: slli t3, t3, 31
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# CHECK: encoding: [0x13,0x1e,0xfe,0x01]
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slli t3, t3, 31
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# CHECK-INST: srli a0, a4, 0
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# CHECK: encoding: [0x13,0x55,0x07,0x00]
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srli a0, a4, 0
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# CHECK-INST: srai a2, sp, 15
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# CHECK: encoding: [0x13,0x56,0xf1,0x40]
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srai a2, sp, 15
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# CHECK-INST: add ra, zero, zero
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# CHECK: encoding: [0xb3,0x00,0x00,0x00]
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add ra, zero, zero
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# CHECK-INST: add ra, zero, zero
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# CHECK: encoding: [0xb3,0x00,0x00,0x00]
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add x1, x0, x0
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# CHECK-INST: sub t0, t2, t1
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# CHECK: encoding: [0xb3,0x82,0x63,0x40]
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sub t0, t2, t1
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# CHECK-INST: sll a5, a4, a3
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# CHECK: encoding: [0xb3,0x17,0xd7,0x00]
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sll a5, a4, a3
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# CHECK-INST: slt s0, s0, s0
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# CHECK: encoding: [0x33,0x24,0x84,0x00]
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slt s0, s0, s0
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# CHECK-INST: sltu gp, a0, a1
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# CHECK: encoding: [0xb3,0x31,0xb5,0x00]
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sltu gp, a0, a1
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# CHECK-INST: xor s2, s2, s8
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# CHECK: encoding: [0x33,0x49,0x89,0x01]
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xor s2, s2, s8
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# CHECK-INST: xor s2, s2, s8
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# CHECK: encoding: [0x33,0x49,0x89,0x01]
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xor x18, x18, x24
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# CHECK-INST: srl a0, s0, t0
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# CHECK: encoding: [0x33,0x55,0x54,0x00]
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srl a0, s0, t0
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# CHECK-INST: sra t0, s2, zero
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# CHECK: encoding: [0xb3,0x52,0x09,0x40]
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sra t0, s2, zero
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# CHECK-INST: or s10, t1, ra
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# CHECK: encoding: [0x33,0x6d,0x13,0x00]
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or s10, t1, ra
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# CHECK-INST: and a0, s2, s3
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# CHECK: encoding: [0x33,0x75,0x39,0x01]
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and a0, s2, s3
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# CHECK-INST: fence iorw, iorw
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# CHECK: encoding: [0x0f,0x00,0xf0,0x0f]
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fence iorw, iorw
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# CHECK-INST: fence io, rw
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# CHECK: encoding: [0x0f,0x00,0x30,0x0c]
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fence io, rw
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# CHECK-INST: fence r, w
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# CHECK: encoding: [0x0f,0x00,0x10,0x02]
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fence r,w
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# CHECK-INST: fence w, ir
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# CHECK: encoding: [0x0f,0x00,0xa0,0x01]
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fence w,ir
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# CHECK-INST: fence.tso
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# CHECK: encoding: [0x0f,0x00,0x30,0x83]
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fence.tso
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# CHECK-INST: fence.i
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# CHECK: encoding: [0x0f,0x10,0x00,0x00]
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fence.i
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# CHECK-INST: ecall
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# CHECK: encoding: [0x73,0x00,0x00,0x00]
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ecall
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# CHECK-INST: ebreak
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# CHECK: encoding: [0x73,0x00,0x10,0x00]
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ebreak
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# CHECK-INST: csrrw t0, 4095, t1
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# CHECK: encoding: [0xf3,0x12,0xf3,0xff]
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csrrw t0, 0xfff, t1
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# CHECK-INST: csrrs s0, 3072, zero
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# CHECK: encoding: [0x73,0x24,0x00,0xc0]
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csrrs s0, 0xc00, x0
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# CHECK-INST: csrrs s3, 1, s5
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# CHECK: encoding: [0xf3,0xa9,0x1a,0x00]
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csrrs s3, 0x001, s5
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# CHECK-INST: csrrc sp, 0, ra
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# CHECK: encoding: [0x73,0xb1,0x00,0x00]
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csrrc sp, 0x000, ra
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# CHECK-INST: csrrwi a5, 0, 0
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# CHECK: encoding: [0xf3,0x57,0x00,0x00]
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csrrwi a5, 0x000, 0
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# CHECK-INST: csrrsi t2, 4095, 31
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# CHECK: encoding: [0xf3,0xe3,0xff,0xff]
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csrrsi t2, 0xfff, 31
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# CHECK-INST: csrrci t1, 320, 5
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# CHECK: encoding: [0x73,0xf3,0x02,0x14]
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csrrci t1, 0x140, 5
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