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The DataLayout can calculate alignment of vectors based on the alignment of the element type and the number of elements. In fact, it is the product of these two values. The problem is that for vectors of N x i1, this will return the alignment of N bytes, since the alignment of i1 is 8 bits. The vector types of vNi1 should be aligned to N bits instead. Provide explicit alignment for HVX vectors to avoid such complications. llvm-svn: 260678
39 lines
1.3 KiB
LLVM
39 lines
1.3 KiB
LLVM
; RUN: llc -march=hexagon -mcpu=hexagonv60 -enable-hexagon-hvx < %s \
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; RUN: | FileCheck %s
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; Check that the store to Q6VecPredResult does not get expanded into multiple
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; stores. There should be no memd's. This relies on the alignment specified
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; in the data layout string, so don't provide one here to make sure that the
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; default one from HexagonTargetMachine is correct.
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; CHECK-NOT: memd
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@Q6VecPredResult = common global <16 x i32> zeroinitializer, align 64
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; Function Attrs: nounwind
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define i32 @foo() #0 {
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entry:
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%0 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1)
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%1 = tail call <512 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %0, i32 -2147483648)
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store <512 x i1> %1, <512 x i1>* bitcast (<16 x i32>* @Q6VecPredResult to <512 x i1>*), align 64, !tbaa !1
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tail call void @print_vecpred(i32 64, i8* bitcast (<16 x i32>* @Q6VecPredResult to i8*)) #3
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ret i32 0
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}
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; Function Attrs: nounwind readnone
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declare <512 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1
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declare void @print_vecpred(i32, i8*) #2
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind }
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!1 = !{!2, !2, i64 0}
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!2 = !{!"omnipotent char", !3, i64 0}
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!3 = !{!"Simple C/C++ TBAA"}
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