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7f4a227354
Summary: Since pointers are 32-bit on x32 we can use ebp and esp as frame and stack pointer. Some operations like PUSH/POP and CFI_INSTRUCTION still require 64-bit register, so using 64-bit MachineFramePtr where required. X86_64 NaCl uses 64-bit frame/stack pointers, however it's been found that both isTarget64BitLP64 and isTarget64BitILP32 are true for NaCl. Addressing this issue here as well by making isTarget64BitLP64 false. Also mark hasReservedSpillSlot unreachable on X86. See inlined comments. Test Plan: Add one new simple test and upgrade 2 existing with x32 target case. Reviewers: nadav, dschuff Subscribers: llvm-commits, zinovy.nis Differential Revision: http://reviews.llvm.org/D4617 llvm-svn: 215091
35 lines
859 B
LLVM
35 lines
859 B
LLVM
; RUN: llc -mtriple=x86_64-pc-linux < %s | FileCheck %s
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; RUN: llc -mtriple=x86_64-pc-linux-gnux32 < %s | FileCheck -check-prefix=X32ABI %s
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; RUN: llc -mtriple=x86_64-pc-nacl < %s | FileCheck -check-prefix=NACL %s
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; x32 uses %esp, %ebp as stack and frame pointers
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; CHECK-LABEL: foo
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; CHECK: pushq %rbp
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; CHECK: movq %rsp, %rbp
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; CHECK: movq %rdi, -8(%rbp)
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; CHECK: popq %rbp
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; X32ABI-LABEL: foo
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; X32ABI: pushq %rbp
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; X32ABI: movl %esp, %ebp
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; X32ABI: movl %edi, -4(%ebp)
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; X32ABI: popq %rbp
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; NACL-LABEL: foo
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; NACL: pushq %rbp
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; NACL: movq %rsp, %rbp
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; NACL: movl %edi, -4(%rbp)
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; NACL: popq %rbp
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define void @foo(i32* %a) #0 {
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entry:
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%a.addr = alloca i32*, align 4
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%b = alloca i32*, align 4
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store i32* %a, i32** %a.addr, align 4
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ret void
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}
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attributes #0 = { nounwind uwtable "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"}
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