mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-26 22:42:46 +02:00
c67d7f29c0
null. For some reason some of the original TTI code supported a null target machine. This seems to have been legacy, and I made matters worse when refactoring this code by spreading that pattern further through the various targets. The TargetMachine can't actually be null, and it doesn't make sense to support that use case. I've now consistently removed it and removed all of the code trying to cope with that situation. This is probably good, as several targets *didn't* cope with it being null despite the null default argument in their constructors. =] llvm-svn: 227734
129 lines
3.8 KiB
C++
129 lines
3.8 KiB
C++
//===-- ARMTargetTransformInfo.h - ARM specific TTI -------------*- C++ -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
/// \file
|
|
/// This file a TargetTransformInfo::Concept conforming object specific to the
|
|
/// ARM target machine. It uses the target's detailed information to
|
|
/// provide more precise answers to certain TTI queries, while letting the
|
|
/// target independent and default TTI implementations handle the rest.
|
|
///
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
|
|
#define LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
|
|
|
|
#include "ARM.h"
|
|
#include "ARMTargetMachine.h"
|
|
#include "llvm/Analysis/TargetTransformInfo.h"
|
|
#include "llvm/CodeGen/BasicTTIImpl.h"
|
|
#include "llvm/Target/TargetLowering.h"
|
|
|
|
namespace llvm {
|
|
|
|
class ARMTTIImpl : public BasicTTIImplBase<ARMTTIImpl> {
|
|
typedef BasicTTIImplBase<ARMTTIImpl> BaseT;
|
|
typedef TargetTransformInfo TTI;
|
|
|
|
const ARMSubtarget *ST;
|
|
const ARMTargetLowering *TLI;
|
|
|
|
/// Estimate the overhead of scalarizing an instruction. Insert and Extract
|
|
/// are set if the result needs to be inserted and/or extracted from vectors.
|
|
unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract);
|
|
|
|
public:
|
|
explicit ARMTTIImpl(const ARMBaseTargetMachine *TM)
|
|
: BaseT(TM), ST(TM->getSubtargetImpl()), TLI(ST->getTargetLowering()) {}
|
|
|
|
// Provide value semantics. MSVC requires that we spell all of these out.
|
|
ARMTTIImpl(const ARMTTIImpl &Arg)
|
|
: BaseT(static_cast<const BaseT &>(Arg)), ST(Arg.ST), TLI(Arg.TLI) {}
|
|
ARMTTIImpl(ARMTTIImpl &&Arg)
|
|
: BaseT(std::move(static_cast<BaseT &>(Arg))), ST(std::move(Arg.ST)),
|
|
TLI(std::move(Arg.TLI)) {}
|
|
ARMTTIImpl &operator=(const ARMTTIImpl &RHS) {
|
|
BaseT::operator=(static_cast<const BaseT &>(RHS));
|
|
ST = RHS.ST;
|
|
TLI = RHS.TLI;
|
|
return *this;
|
|
}
|
|
ARMTTIImpl &operator=(ARMTTIImpl &&RHS) {
|
|
BaseT::operator=(std::move(static_cast<BaseT &>(RHS)));
|
|
ST = std::move(RHS.ST);
|
|
TLI = std::move(RHS.TLI);
|
|
return *this;
|
|
}
|
|
|
|
/// \name Scalar TTI Implementations
|
|
/// @{
|
|
|
|
using BaseT::getIntImmCost;
|
|
unsigned getIntImmCost(const APInt &Imm, Type *Ty);
|
|
|
|
/// @}
|
|
|
|
/// \name Vector TTI Implementations
|
|
/// @{
|
|
|
|
unsigned getNumberOfRegisters(bool Vector) {
|
|
if (Vector) {
|
|
if (ST->hasNEON())
|
|
return 16;
|
|
return 0;
|
|
}
|
|
|
|
if (ST->isThumb1Only())
|
|
return 8;
|
|
return 13;
|
|
}
|
|
|
|
unsigned getRegisterBitWidth(bool Vector) {
|
|
if (Vector) {
|
|
if (ST->hasNEON())
|
|
return 128;
|
|
return 0;
|
|
}
|
|
|
|
return 32;
|
|
}
|
|
|
|
unsigned getMaxInterleaveFactor() {
|
|
// These are out of order CPUs:
|
|
if (ST->isCortexA15() || ST->isSwift())
|
|
return 2;
|
|
return 1;
|
|
}
|
|
|
|
unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index,
|
|
Type *SubTp);
|
|
|
|
unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src);
|
|
|
|
unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy);
|
|
|
|
unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
|
|
|
|
unsigned getAddressComputationCost(Type *Val, bool IsComplex);
|
|
|
|
unsigned getArithmeticInstrCost(
|
|
unsigned Opcode, Type *Ty,
|
|
TTI::OperandValueKind Op1Info = TTI::OK_AnyValue,
|
|
TTI::OperandValueKind Op2Info = TTI::OK_AnyValue,
|
|
TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
|
|
TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None);
|
|
|
|
unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
|
|
unsigned AddressSpace);
|
|
|
|
/// @}
|
|
};
|
|
|
|
} // end namespace llvm
|
|
|
|
#endif
|