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https://github.com/RPCS3/llvm-mirror.git
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166 lines
3.9 KiB
LLVM
166 lines
3.9 KiB
LLVM
; RUN: opt -insert-edge-profiling -o %t1 < %s
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; RUN: rm -f %t1.prof_data
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; RUN: lli %defaultjit -load %llvmshlibdir/libprofile_rt%shlibext %t1 \
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; RUN: -llvmprof-output %t1.prof_data
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; RUN: opt -profile-file %t1.prof_data -profile-metadata-loader -S -o - < %s \
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; RUN: | FileCheck %s
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; RUN: rm -f %t1.prof_data
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; FIXME: profile_rt.dll could be built on win32.
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; REQUIRES: loadable_module
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;; func_switch - Test branch probabilities for a switch instruction with an
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;; even chance of taking each case (or no case).
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define i32 @func_switch(i32 %N) nounwind uwtable {
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entry:
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%retval = alloca i32, align 4
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%N.addr = alloca i32, align 4
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store i32 %N, i32* %N.addr, align 4
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%0 = load i32* %N.addr, align 4
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%rem = srem i32 %0, 4
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switch i32 %rem, label %sw.epilog [
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i32 0, label %sw.bb
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i32 1, label %sw.bb1
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i32 2, label %sw.bb2
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]
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; CHECK: ], !prof !0
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sw.bb:
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store i32 5, i32* %retval
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br label %return
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sw.bb1:
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store i32 6, i32* %retval
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br label %return
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sw.bb2:
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store i32 7, i32* %retval
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br label %return
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sw.epilog:
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store i32 8, i32* %retval
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br label %return
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return:
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%1 = load i32* %retval
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ret i32 %1
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}
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;; func_switch_switch - Test branch probabilities in a switch-instruction that
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;; leads to further switch instructions. The first-tier switch occludes some
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;; possibilities in the second-tier switches, leading to some branches having a
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;; 0 probability.
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define i32 @func_switch_switch(i32 %N) nounwind uwtable {
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entry:
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%retval = alloca i32, align 4
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%N.addr = alloca i32, align 4
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store i32 %N, i32* %N.addr, align 4
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%0 = load i32* %N.addr, align 4
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%rem = srem i32 %0, 2
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switch i32 %rem, label %sw.default11 [
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i32 0, label %sw.bb
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i32 1, label %sw.bb5
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]
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; CHECK: ], !prof !1
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sw.bb:
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%1 = load i32* %N.addr, align 4
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%rem1 = srem i32 %1, 4
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switch i32 %rem1, label %sw.default [
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i32 0, label %sw.bb2
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i32 1, label %sw.bb3
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i32 2, label %sw.bb4
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]
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; CHECK: ], !prof !2
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sw.bb2:
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store i32 5, i32* %retval
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br label %return
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sw.bb3:
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store i32 6, i32* %retval
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br label %return
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sw.bb4:
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store i32 7, i32* %retval
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br label %return
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sw.default:
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store i32 8, i32* %retval
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br label %return
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sw.bb5:
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%2 = load i32* %N.addr, align 4
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%rem6 = srem i32 %2, 4
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switch i32 %rem6, label %sw.default10 [
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i32 0, label %sw.bb7
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i32 1, label %sw.bb8
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i32 2, label %sw.bb9
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]
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; CHECK: ], !prof !3
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sw.bb7:
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store i32 9, i32* %retval
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br label %return
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sw.bb8:
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store i32 10, i32* %retval
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br label %return
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sw.bb9:
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store i32 11, i32* %retval
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br label %return
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sw.default10:
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store i32 12, i32* %retval
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br label %return
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sw.default11:
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store i32 13, i32* %retval
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br label %return
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return:
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%3 = load i32* %retval
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ret i32 %3
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}
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define i32 @main(i32 %argc, i8** %argv) nounwind uwtable {
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entry:
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%retval = alloca i32, align 4
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%argc.addr = alloca i32, align 4
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%argv.addr = alloca i8**, align 8
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%loop = alloca i32, align 4
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store i32 0, i32* %retval
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store i32 0, i32* %loop, align 4
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br label %for.cond
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for.cond:
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%0 = load i32* %loop, align 4
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%cmp = icmp slt i32 %0, 4000
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br i1 %cmp, label %for.body, label %for.end
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; CHECK: br i1 %cmp, label %for.body, label %for.end, !prof !4
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for.body:
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%1 = load i32* %loop, align 4
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%call = call i32 @func_switch(i32 %1)
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%2 = load i32* %loop, align 4
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%call1 = call i32 @func_switch_switch(i32 %2)
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br label %for.inc
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for.inc:
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%3 = load i32* %loop, align 4
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%inc = add nsw i32 %3, 1
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store i32 %inc, i32* %loop, align 4
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br label %for.cond
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for.end:
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ret i32 0
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}
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; CHECK: !0 = metadata !{metadata !"branch_weights", i32 1000, i32 1000, i32 1000, i32 1000}
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; CHECK: !1 = metadata !{metadata !"branch_weights", i32 0, i32 2000, i32 2000}
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; CHECK: !2 = metadata !{metadata !"branch_weights", i32 0, i32 1000, i32 0, i32 1000}
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; CHECK: !3 = metadata !{metadata !"branch_weights", i32 1000, i32 0, i32 1000, i32 0}
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; CHECK: !4 = metadata !{metadata !"branch_weights", i32 4000, i32 1}
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; CHECK-NOT: !5
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