Gadi Haber c6fb224953 [X86][Skylake] Adding the scheduling information for the SkylakeClient target ... This patch adds the instruction scheduling information for the SkylakeClient (SKL) architecture target by adding the file X86SchedSkylakeClient.td located under the X86 Target. We used the scheduling information retrieved from the Skylake architects in order to create the file. The scheduling information includes latency, number of micro-Ops and used ports by each SKL instruction. The patch continues the scheduling replacement and insertion effort started with the SNB target in r307529 and r310792 and for HSW in r311879. Please expect some performance fluctuations due to code alignment effects. Reviewers: craig.topper, zvi, chandlerc, igorb, aymanmus, RKSimon, delena Differential Revision: https://reviews.llvm.org/D37294 llvm-svn: 313613		2017-09-19 06:19:27 +00:00
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AArch64	[LoopVectorizer] Add more testcases for PR33804.	2017-09-18 17:28:15 +00:00
AMDGPU	AMDGPU: Start selecting s_xnor_{b32, b64}	2017-09-18 21:22:45 +00:00
ARC
ARM	[LoopVectorizer] Add more testcases for PR33804.	2017-09-18 17:28:15 +00:00
AVR
BPF	bpf: add inline-asm support	2017-09-18 23:29:36 +00:00
Generic
Hexagon	[IfConversion] More simple, correct dead/kill liveness handling	2017-09-14 15:53:11 +00:00
Inputs
Lanai
Mips	[mips] Pick the right variant of DINS upfront and enable target instruction verification	2017-09-14 10:58:00 +00:00
MIR
MSP430
Nios2
NVPTX
PowerPC	[XRay][CodeGen] Use the current function symbol as the associated symbol for the instrumentation map	2017-09-14 07:08:23 +00:00
SPARC
SystemZ	Move llvm/test/CodeGen/X86/clear-liverange-spillreg.mir to SystemZ. It was in wrong place.	2017-09-14 00:03:23 +00:00
Thumb
Thumb2
WebAssembly	[WebAssembly] Add sign extend instructions from atomics proposal	2017-09-13 00:29:06 +00:00
WinEH
X86	[X86][Skylake] Adding the scheduling information for the SkylakeClient target	2017-09-19 06:19:27 +00:00
XCore