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https://github.com/RPCS3/llvm-mirror.git
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c7055f98bf
Add a pass to remove redundant S_OR_B64 instructions enabling lanes in the exec. If two SI_END_CF (lowered as S_OR_B64) come together without any vector instructions between them we can only keep outer SI_END_CF, given that CFG is structured and exec bits of the outer end statement are always not less than exec bit of the inner one. This needs to be done before the RA to eliminate saved exec bits registers but after register coalescer to have no vector registers copies in between of different end cf statements. Differential Revision: https://reviews.llvm.org/D35967 llvm-svn: 309762
117 lines
3.3 KiB
CMake
117 lines
3.3 KiB
CMake
set(LLVM_TARGET_DEFINITIONS AMDGPU.td)
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tablegen(LLVM AMDGPUGenRegisterInfo.inc -gen-register-info)
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tablegen(LLVM AMDGPUGenInstrInfo.inc -gen-instr-info)
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tablegen(LLVM AMDGPUGenDAGISel.inc -gen-dag-isel)
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tablegen(LLVM AMDGPUGenCallingConv.inc -gen-callingconv)
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tablegen(LLVM AMDGPUGenSubtargetInfo.inc -gen-subtarget)
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tablegen(LLVM AMDGPUGenIntrinsics.inc -gen-tgt-intrinsic)
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tablegen(LLVM AMDGPUGenMCCodeEmitter.inc -gen-emitter)
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tablegen(LLVM AMDGPUGenDFAPacketizer.inc -gen-dfa-packetizer)
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tablegen(LLVM AMDGPUGenAsmWriter.inc -gen-asm-writer)
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tablegen(LLVM AMDGPUGenAsmMatcher.inc -gen-asm-matcher)
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tablegen(LLVM AMDGPUGenDisassemblerTables.inc -gen-disassembler)
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tablegen(LLVM AMDGPUGenMCPseudoLowering.inc -gen-pseudo-lowering)
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if(LLVM_BUILD_GLOBAL_ISEL)
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tablegen(LLVM AMDGPUGenRegisterBank.inc -gen-register-bank)
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endif()
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add_public_tablegen_target(AMDGPUCommonTableGen)
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# List of all GlobalISel files.
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set(GLOBAL_ISEL_FILES
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AMDGPUCallLowering.cpp
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AMDGPUInstructionSelector.cpp
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AMDGPULegalizerInfo.cpp
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AMDGPURegisterBankInfo.cpp
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)
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# Add GlobalISel files to the dependencies if the user wants to build it.
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if(LLVM_BUILD_GLOBAL_ISEL)
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set(GLOBAL_ISEL_BUILD_FILES ${GLOBAL_ISEL_FILES})
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else()
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set(GLOBAL_ISEL_BUILD_FILES"")
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set(LLVM_OPTIONAL_SOURCES LLVMGlobalISel ${GLOBAL_ISEL_FILES})
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endif()
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add_llvm_target(AMDGPUCodeGen
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AMDILCFGStructurizer.cpp
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AMDGPUAliasAnalysis.cpp
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AMDGPUAlwaysInlinePass.cpp
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AMDGPUAnnotateKernelFeatures.cpp
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AMDGPUAnnotateUniformValues.cpp
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AMDGPUAsmPrinter.cpp
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AMDGPUCodeGenPrepare.cpp
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AMDGPUFrameLowering.cpp
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AMDGPUTargetObjectFile.cpp
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AMDGPUIntrinsicInfo.cpp
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AMDGPUISelDAGToDAG.cpp
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AMDGPULowerIntrinsics.cpp
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AMDGPUMacroFusion.cpp
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AMDGPUMCInstLower.cpp
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AMDGPUMachineCFGStructurizer.cpp
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AMDGPUMachineFunction.cpp
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AMDGPUMachineModuleInfo.cpp
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AMDGPUUnifyMetadata.cpp
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AMDGPUOpenCLImageTypeLoweringPass.cpp
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AMDGPUSubtarget.cpp
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AMDGPUTargetMachine.cpp
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AMDGPUTargetTransformInfo.cpp
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AMDGPUISelLowering.cpp
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AMDGPUInstrInfo.cpp
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AMDGPUPromoteAlloca.cpp
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AMDGPURegAsmNames.inc.cpp
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AMDGPURegisterInfo.cpp
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AMDGPURewriteOutArguments.cpp
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AMDGPUUnifyDivergentExitNodes.cpp
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GCNHazardRecognizer.cpp
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GCNSchedStrategy.cpp
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R600ClauseMergePass.cpp
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R600ControlFlowFinalizer.cpp
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R600EmitClauseMarkers.cpp
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R600ExpandSpecialInstrs.cpp
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R600FrameLowering.cpp
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R600InstrInfo.cpp
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R600ISelLowering.cpp
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R600MachineFunctionInfo.cpp
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R600MachineScheduler.cpp
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R600OptimizeVectorRegisters.cpp
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R600Packetizer.cpp
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R600RegisterInfo.cpp
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SIAnnotateControlFlow.cpp
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SIDebuggerInsertNops.cpp
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SIFixControlFlowLiveIntervals.cpp
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SIFixSGPRCopies.cpp
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SIFixVGPRCopies.cpp
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SIFoldOperands.cpp
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SIFrameLowering.cpp
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SIInsertSkips.cpp
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SIInsertWaits.cpp
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SIInsertWaitcnts.cpp
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SIInstrInfo.cpp
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SIISelLowering.cpp
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SILoadStoreOptimizer.cpp
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SILowerControlFlow.cpp
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SILowerI1Copies.cpp
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SIMachineFunctionInfo.cpp
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SIMachineScheduler.cpp
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SIMemoryLegalizer.cpp
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SIOptimizeExecMasking.cpp
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SIOptimizeExecMaskingPreRA.cpp
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SIPeepholeSDWA.cpp
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SIRegisterInfo.cpp
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SIShrinkInstructions.cpp
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SIWholeQuadMode.cpp
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GCNIterativeScheduler.cpp
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GCNMinRegStrategy.cpp
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GCNRegPressure.cpp
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${GLOBAL_ISEL_BUILD_FILES}
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)
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add_subdirectory(AsmParser)
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add_subdirectory(InstPrinter)
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add_subdirectory(Disassembler)
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add_subdirectory(TargetInfo)
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add_subdirectory(MCTargetDesc)
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add_subdirectory(Utils)
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