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a39ea3408e
The UDF instruction is a reserved undefined instruction space. The assembler mnemonic was introduced with ARM ARM rev C.a. The instruction is not predicated and the immediate constant is ignored by the CPU. Add support for the three encodings for this instruction. The changes to the invalid instruction test is due to the fact that the invalid instructions actually overlap with the undefined instruction. Introduction of the new instruction results in a partial decode as an undefined sequence. Drop the tests as they are invalid instruction patterns anyways. llvm-svn: 208751
369 lines
14 KiB
Plaintext
369 lines
14 KiB
Plaintext
# RUN: not llvm-mc -disassemble %s -mcpu cortex-a8 -triple thumbv7 2>&1 | FileCheck %s
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# This file is checking Thumbv7 encodings which are globally invalid, usually due
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# to the constraints of the instructions not being met. For example invalid
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# combinations of registers.
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#------------------------------------------------------------------------------
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# Undefined encoding for b.cc
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#------------------------------------------------------------------------------
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# Opcode=1894 Name=t2Bcc Format=ARM_FORMAT_THUMBFRM(25)
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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# -------------------------------------------------------------------------------------------------
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# | 1: 1: 1: 1| 0: 1: 1: 1| 1: 0: 1: 0| 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 1: 1| 0: 1: 0: 0| 0: 1: 0: 0|
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# -------------------------------------------------------------------------------------------------
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#
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# A8.6.16 B
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# if cond<3:1> == '111' then SEE "Related Encodings"
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[0xaf 0xf7 0x44 0x8b]
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# CHECK: warning: invalid instruction encoding
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# CHECK-NEXT: [0xaf 0xf7 0x44 0x8b]
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#------------------------------------------------------------------------------
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# Undefined encoding for it
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#------------------------------------------------------------------------------
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[0xff 0xbf 0x6b 0x80 0x00 0x75]
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# CHECK: potentially undefined instruction encoding
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# CHECK-NEXT: [0xff 0xbf 0x6b 0x80 0x00 0x75]
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[0x50 0xbf] # hint #5; legal as the third instruction for the iteee above
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# Two warnings from this block since there are two instructions in there
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[0xdb 0xbf 0x42 0xbb]
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# CHECK: potentially undefined instruction encoding
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# CHECK-NEXT: [0xdb 0xbf 0x42 0xbb]
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# CHECK: potentially undefined instruction encoding
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# CHECK-NEXT: [0xdb 0xbf 0x42 0xbb]
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#------------------------------------------------------------------------------
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# Undefined encoding for ldm
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#------------------------------------------------------------------------------
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# Writeback is not allowed is Rn is in the target register list.
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[0xb4 0xe8 0x34 0x04]
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# CHECK: potentially undefined instruction encoding
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# CHECK-NEXT: [0xb4 0xe8 0x34 0x04]
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#------------------------------------------------------------------------------
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# Undefined encoding for ldrd
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#------------------------------------------------------------------------------
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# Opcode=1930 Name=t2LDRD_PRE Format=ARM_FORMAT_THUMBFRM(25)
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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# -------------------------------------------------------------------------------------------------
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# | 1: 1: 1: 0| 1: 0: 0: 1| 1: 1: 1: 1| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0|
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# -------------------------------------------------------------------------------------------------
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#
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# A8.6.66 LDRD (immediate)
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# if Rn = '1111' then SEE LDRD (literal)
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# A8.6.67 LDRD (literal)
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# Inst{21} = 0
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[0xff 0xe9 0x0 0xeb]
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# CHECK: potentially undefined
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# CHECK-NEXT: [0xff 0xe9 0x0 0xeb]
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#------------------------------------------------------------------------------
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# Undefined encodings for ldrbt
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#------------------------------------------------------------------------------
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# Opcode=1922 Name=t2LDRBT Format=ARM_FORMAT_THUMBFRM(25)
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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# -------------------------------------------------------------------------------------------------
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# | 1: 1: 1: 1| 1: 0: 0: 0| 0: 0: 0: 1| 0: 0: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 0: 0: 0: 0| 0: 0: 1: 1|
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# -------------------------------------------------------------------------------------------------
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#
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# The unpriviledged Load/Store cannot have SP or PC as Rt.
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[0x10 0xf8 0x3 0xfe]
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# CHECK: potentially undefined instruction encoding
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# CHECK-NEXT: [0x10 0xf8 0x3 0xfe]
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#------------------------------------------------------------------------------
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# Undefined encodings for ldrsh
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#------------------------------------------------------------------------------
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# invalid LDRSHs Rt=PC
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[0x30 0xf9 0x00 0xf0]
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x30 0xf9 0x00 0xf0]
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# invalid LDRSHi8 Rt=PC
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[0x30 0xf9 0x00 0xfc]
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x30 0xf9 0x00 0xfc]
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# invalid LDRSHi12 Rt=PC
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[0xb0 0xf9 0x00 0xf0]
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0xb0 0xf9 0x00 0xf0]
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# Opcode=1954 Name=t2LDRSHi8 Format=ARM_FORMAT_THUMBFRM(25)
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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# -------------------------------------------------------------------------------------------------
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# | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 1: 1| 0: 1: 0: 1| 1: 1: 1: 1| 1: 1: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0|
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# -------------------------------------------------------------------------------------------------
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#
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# if Rt == '1111' and PUW == '100' then SEE "Unallocated memory hints"
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[0x35 0xf9 0x00 0xfc]
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x35 0xf9 0x00 0xfc]
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# Opcode=1953 Name=t2LDRSHi12 Format=ARM_FORMAT_THUMBFRM(25)
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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# -------------------------------------------------------------------------------------------------
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# | 1: 1: 1: 1| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 1| 1: 1: 1: 1|
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# -------------------------------------------------------------------------------------------------
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#
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# if Rt = '1111' then SEE "Unallocated memory hints"
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[0xb3 0xf9 0xdf 0xf8]
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0xb3 0xf9 0xdf 0xf8]
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#------------------------------------------------------------------------------
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# Undefined encoding for push
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#------------------------------------------------------------------------------
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# SP and PC are not allowed in the register list on STM instructions in Thumb2.
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[0x2d 0xe9 0xf7 0xb6]
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x2d 0xe9 0xf7 0xb6]
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#------------------------------------------------------------------------------
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# Undefined encoding for stmia
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#------------------------------------------------------------------------------
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# Opcode=2313 Name=tSTMIA_UPD Format=ARM_FORMAT_THUMBFRM(25)
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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# -------------------------------------------------------------------------------------------------
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# | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 0| 0: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0|
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# -------------------------------------------------------------------------------------------------
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#
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# if BitCount(registers) < 1 then UNPREDICTABLE
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[0x00 0xc7]
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x00 0xc7]
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#------------------------------------------------------------------------------
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# Undefined encodings for str
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#------------------------------------------------------------------------------
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# invalid STRi12 Rn=PC
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[0xcf 0xf8 0x00 0x00]
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0xcf 0xf8 0x00 0x00]
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# invalid STRi8 Rn=PC
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[0x4f 0xf8 0x00 0x0c]
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x4f 0xf8 0x00 0x0c]
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# invalid STRs Rn=PC
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[0x4f 0xf8 0x00 0x00]
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x4f 0xf8 0x00 0x00]
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# invalid STRBi12 Rn=PC
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[0x0f 0xf8 0x00 0x00]
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x0f 0xf8 0x00 0x00]
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# invalid STRBi8 Rn=PC
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[0x0f 0xf8 0x00 0x0c]
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x0f 0xf8 0x00 0x0c]
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# invalid STRBs Rn=PC
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[0x0f 0xf8 0x00 0x00]
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x0f 0xf8 0x00 0x00]
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# invalid STRHi12 Rn=PC
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[0xaf 0xf8 0x00 0x00]
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0xaf 0xf8 0x00 0x00]
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# invalid STRHi8 Rn=PC
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[0x2f 0xf8 0x00 0x0c]
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x2f 0xf8 0x00 0x0c]
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# invalid STRHs Rn=PC
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[0x2f 0xf8 0x00 0x00]
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x2f 0xf8 0x00 0x00]
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# invalid STRBT Rn=PC
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[0x0f 0xf8 0x00 0x0e]
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x0f 0xf8 0x00 0x0e]
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# invalid STRHT Rn=PC
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[0x2f 0xf8 0x00 0x0e]
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x2f 0xf8 0x00 0x0e]
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# invalid STRT Rn=PC
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[0x4f 0xf8 0x00 0x0e]
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x4f 0xf8 0x00 0x0e]
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# Opcode=2137 Name=t2STR_POST Format=ARM_FORMAT_THUMBFRM(25)
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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# -------------------------------------------------------------------------------------------------
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# | 1: 1: 1: 1| 1: 0: 0: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 1: 1: 1: 1| 1: 1: 1: 1|
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# -------------------------------------------------------------------------------------------------
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#
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# if Rn == '1111' then UNDEFINED
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[0x4f 0xf8 0xff 0xeb]
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x4f 0xf8 0xff 0xeb]
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#------------------------------------------------------------------------------
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# Undefined encodings for strd
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#------------------------------------------------------------------------------
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# Rt == Rn is UNPREDICTABLE
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[0xe4 0xe9 0x02 0x46]
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# CHECK: warning: potentially undefined instruction encoding
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# CHECK-NEXT: [0xe4 0xe9 0x02 0x46]
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#------------------------------------------------------------------------------
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# Undefined encodings for NEON vld instructions
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#------------------------------------------------------------------------------
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# size = '00' and index_align == '0001' so UNDEFINED
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[0xa0 0xf9 0x10 0x08]
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0xa0 0xf9 0x10 0x08]
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# vld3
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# Opcode=871 Name=VLD3DUPd32_UPD Format=ARM_FORMAT_NLdSt(30)
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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# -------------------------------------------------------------------------------------------------
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# | 1: 1: 1: 1| 0: 1: 0: 0| 1: 0: 1: 0| 0: 0: 1: 0| 0: 0: 1: 0| 1: 1: 1: 0| 1: 0: 0: 1| 0: 0: 1: 0|
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# -------------------------------------------------------------------------------------------------
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#
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# A8.6.315 VLD3 (single 3-element structure to all lanes)
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# The a bit must be encoded as 0.
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[0xa2 0xf9 0x92 0x2e]
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0xa2 0xf9 0x92 0x2e]
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# Some vld4 ones
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# size == '11' and a == '0' so UNDEFINED
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[0xa0 0xf9 0xc0 0x0f]
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0xa0 0xf9 0xc0 0x0f]
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[0xa0 0xf9 0x30 0x0b]
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0xa0 0xf9 0x30 0x0b]
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# VLD1 multi-element, type=0b1010 align=0b11
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[0x24 0xf9 0xbf 0x8a]
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x24 0xf9 0xbf 0x8a]
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# VLD1 multi-element type=0b0111 align=0b1x
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[0x24 0xf9 0xbf 0x87]
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x24 0xf9 0xbf 0x87]
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# VLD1 multi-element type=0b0010 align=0b1x
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[0x24 0xf9 0xbf 0x86]
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x24 0xf9 0xbf 0x86]
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# VLD2 multi-element size=0b11
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[0x60 0xf9 0xcf 0x08]
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x60 0xf9 0xcf 0x08]
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# VLD2 multi-element type=0b1111 align=0b11
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[0x60 0xf9 0xbf 0x08]
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x60 0xf9 0xbf 0x08]
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# VLD2 multi-element type=0b1001 align=0b11
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[0x60 0xf9 0xbf 0x09]
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x60 0xf9 0xbf 0x09]
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# VLD3 multi-element size=0b11
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[0x60 0xf9 0x7f 0x04]
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x60 0xf9 0x7f 0x04]
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# VLD3 multi-element align=0b1x
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[0x60 0xf9 0xcf 0x04]
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x60 0xf9 0xcf 0x04]
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# VLD4 multi-element size=0b11
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[0x60 0xf9 0xcd 0x11]
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x60 0xf9 0xcd 0x11]
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#------------------------------------------------------------------------------
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# Undefined encodings for NEON vst1
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#------------------------------------------------------------------------------
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# size == '10' and index_align == '0001' so UNDEFINED
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[0x80 0xf9 0x10 0x08]
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x80 0xf9 0x10 0x08]
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# Opcode=1839 Name=VST1d8Twb_register Format=ARM_FORMAT_NLdSt(30)
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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# -------------------------------------------------------------------------------------------------
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# | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 1: 0| 0: 0: 1: 0| 1: 1: 1: 1|
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# -------------------------------------------------------------------------------------------------
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#
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# A8.6.391 VST1 (multiple single elements)
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# This encoding looks like: vst1.8 {d0,d1,d2}, [r0:128]
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# But bits 5-4 for the alignment of 128 encoded as align = 0b10, is available only if <list>
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# contains two or four registers. rdar://11220250
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[0x00 0xf9 0x2f 0x06]
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x00 0xf9 0x2f 0x06]
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#------------------------------------------------------------------------------
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# Undefined encodings for NEON vst4
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#------------------------------------------------------------------------------
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[0x80 0xf9 0x30 0x0b]
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x80 0xf9 0x30 0x0b]
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#------------------------------------------------------------------------------
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# Unpredictable STMs
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#------------------------------------------------------------------------------
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# 32-bit Thumb STM instructions cannot have a writeback register which appears
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# in the list.
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[0xa1,0xe8,0x07,0x04]
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# CHECK: warning: potentially undefined instruction encoding
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# CHECK-NEXT: [0xa1,0xe8,0x07,0x04]
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[0x21,0xe9,0x07,0x04]
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# CHECK: warning: potentially undefined instruction encoding
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# CHECK-NEXT: [0x21,0xe9,0x07,0x04]
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