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11fab31200
Due to an erratum in some versions of LEON, we must insert a NOP after any LD or LDF instruction to ensure the processor has time to load the value correctly before using it. This pass will implement that erratum fix. The code will have no effect for other Sparc, but non-LEON processors. Differential Review: http://reviews.llvm.org/D20353 llvm-svn: 270417
46 lines
1.5 KiB
TableGen
Executable File
46 lines
1.5 KiB
TableGen
Executable File
//===-- LeonFeatures.td - Describe the Leon Features -------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// UMAC and SMAC support for LEON3 and LEON4 processors.
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//===----------------------------------------------------------------------===//
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//support to casa instruction; for leon3 subtarget only
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def UMACSMACSupport : SubtargetFeature<
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"hasumacsmac",
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"HasUmacSmac",
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"true",
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"Enable UMAC and SMAC for LEON3 and LEON4 processors"
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>;
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//===----------------------------------------------------------------------===//
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// CASA Support differs between LEON3-FT GR712RC and LEON3-FT UT699
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// We need to have the option to switch this on and off.
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//===----------------------------------------------------------------------===//
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//support to casa instruction; for leon3 subtarget only
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def LeonCASA : SubtargetFeature<
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"hasleoncasa",
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"HasLeonCasa",
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"true",
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"Enable CASA instruction for LEON3 and LEON4 processors"
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>;
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def InsertNOPLoad: SubtargetFeature<
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"insertnopload",
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"InsertNOPLoad",
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"true",
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"LEON3 erratum fix: Insert a NOP instruction after every single-cycle load instruction when the next instruction is another load/store instruction"
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>;
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