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028d2e0885
Specifically, itineraries for LEON processors has been added, along with several LEON processor Subtargets. Although currently all these targets are pretty much identical, support for features that will differ among these processors will be added in the very near future. The different Instruction Itinerary Classes (IICs) added are sufficient to differentiate between the instruction timings used by LEON and, quite probably, by generic Sparc processors too, but the focus of the exercise has been for LEON processors, as the requirement of my project. If the IICs are not sufficient for other Sparc processor types and you want to add a new itinerary for one of those, it should be relatively trivial to adapt this. As none of the LEON processors has Quad Floats, or is a Version 9 processor, none of those instructions have itinerary classes defined and revert to the default "NoItinerary" instruction itinerary. Phabricator Review: http://reviews.llvm.org/D19359 llvm-svn: 267121
370 lines
10 KiB
TableGen
370 lines
10 KiB
TableGen
//===-- SparcInstrFormats.td - Sparc Instruction Formats ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin = NoItinerary>
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: Instruction {
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field bits<32> Inst;
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let Namespace = "SP";
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let Size = 4;
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bits<2> op;
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let Inst{31-30} = op; // Top two bits are the 'op' field
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dag OutOperandList = outs;
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dag InOperandList = ins;
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let AsmString = asmstr;
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let Pattern = pattern;
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let DecoderNamespace = "Sparc";
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field bits<32> SoftFail = 0;
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let Itinerary = itin;
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}
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//===----------------------------------------------------------------------===//
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// Format #2 instruction classes in the Sparc
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//===----------------------------------------------------------------------===//
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// Format 2 instructions
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class F2<dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin = NoItinerary>
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: InstSP<outs, ins, asmstr, pattern, itin> {
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bits<3> op2;
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bits<22> imm22;
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let op = 0; // op = 0
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let Inst{24-22} = op2;
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let Inst{21-0} = imm22;
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}
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// Specific F2 classes: SparcV8 manual, page 44
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//
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class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin = NoItinerary>
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: F2<outs, ins, asmstr, pattern, itin> {
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bits<5> rd;
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let op2 = op2Val;
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let Inst{29-25} = rd;
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}
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class F2_2<bits<3> op2Val, bit annul, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: F2<outs, ins, asmstr, pattern, itin> {
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bits<4> cond;
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let op2 = op2Val;
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let Inst{29} = annul;
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let Inst{28-25} = cond;
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}
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class F2_3<bits<3> op2Val, bit annul, bit pred,
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dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin = NoItinerary>
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: InstSP<outs, ins, asmstr, pattern, itin> {
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bits<2> cc;
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bits<4> cond;
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bits<19> imm19;
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let op = 0; // op = 0
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let Inst{29} = annul;
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let Inst{28-25} = cond;
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let Inst{24-22} = op2Val;
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let Inst{21-20} = cc;
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let Inst{19} = pred;
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let Inst{18-0} = imm19;
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}
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class F2_4<bits<3> cond, bit annul, bit pred, dag outs, dag ins,
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string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>
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: InstSP<outs, ins, asmstr, pattern, itin> {
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bits<16> imm16;
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bits<5> rs1;
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let op = 0; // op = 0
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let Inst{29} = annul;
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let Inst{28} = 0;
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let Inst{27-25} = cond;
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let Inst{24-22} = 0b011;
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let Inst{21-20} = imm16{15-14};
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let Inst{19} = pred;
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let Inst{18-14} = rs1;
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let Inst{13-0} = imm16{13-0};
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}
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//===----------------------------------------------------------------------===//
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// Format #3 instruction classes in the Sparc
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//===----------------------------------------------------------------------===//
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class F3<dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin = NoItinerary>
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: InstSP<outs, ins, asmstr, pattern, itin> {
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bits<5> rd;
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bits<6> op3;
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bits<5> rs1;
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let op{1} = 1; // Op = 2 or 3
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let Inst{29-25} = rd;
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let Inst{24-19} = op3;
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let Inst{18-14} = rs1;
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}
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// Specific F3 classes: SparcV8 manual, page 44
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//
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class F3_1_asi<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
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string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>
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: F3<outs, ins, asmstr, pattern, itin> {
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bits<8> asi;
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bits<5> rs2;
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let op = opVal;
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let op3 = op3val;
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let Inst{13} = 0; // i field = 0
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let Inst{12-5} = asi; // address space identifier
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let Inst{4-0} = rs2;
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}
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class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin = IIC_iu_instr>
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: F3_1_asi<opVal, op3val, outs, ins, asmstr, pattern, itin> {
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let asi = 0;
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}
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class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
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string asmstr, list<dag> pattern, InstrItinClass itin = IIC_iu_instr>
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: F3<outs, ins, asmstr, pattern, itin> {
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bits<13> simm13;
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let op = opVal;
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let op3 = op3val;
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let Inst{13} = 1; // i field = 1
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let Inst{12-0} = simm13;
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}
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// floating-point
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class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
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string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>
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: F3<outs, ins, asmstr, pattern, itin> {
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bits<5> rs2;
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let op = opVal;
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let op3 = op3val;
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let Inst{13-5} = opfval; // fp opcode
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let Inst{4-0} = rs2;
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}
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// floating-point unary operations.
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class F3_3u<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
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string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>
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: F3<outs, ins, asmstr, pattern, itin> {
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bits<5> rs2;
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let op = opVal;
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let op3 = op3val;
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let rs1 = 0;
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let Inst{13-5} = opfval; // fp opcode
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let Inst{4-0} = rs2;
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}
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// floating-point compares.
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class F3_3c<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
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string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>
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: F3<outs, ins, asmstr, pattern, itin> {
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bits<5> rs2;
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let op = opVal;
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let op3 = op3val;
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let Inst{13-5} = opfval; // fp opcode
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let Inst{4-0} = rs2;
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}
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// Shift by register rs2.
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class F3_Sr<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
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string asmstr, list<dag> pattern, InstrItinClass itin = IIC_iu_instr>
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: F3<outs, ins, asmstr, pattern, itin> {
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bit x = xVal; // 1 for 64-bit shifts.
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bits<5> rs2;
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let op = opVal;
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let op3 = op3val;
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let Inst{13} = 0; // i field = 0
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let Inst{12} = x; // extended registers.
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let Inst{4-0} = rs2;
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}
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// Shift by immediate.
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class F3_Si<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
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string asmstr, list<dag> pattern, InstrItinClass itin = IIC_iu_instr>
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: F3<outs, ins, asmstr, pattern, itin> {
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bit x = xVal; // 1 for 64-bit shifts.
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bits<6> shcnt; // shcnt32 / shcnt64.
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let op = opVal;
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let op3 = op3val;
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let Inst{13} = 1; // i field = 1
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let Inst{12} = x; // extended registers.
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let Inst{5-0} = shcnt;
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}
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// Define rr and ri shift instructions with patterns.
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multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
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ValueType VT, RegisterClass RC,
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InstrItinClass itin = IIC_iu_instr> {
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def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, IntRegs:$rs2),
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!strconcat(OpcStr, " $rs1, $rs2, $rd"),
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[(set VT:$rd, (OpNode VT:$rs1, i32:$rs2))],
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itin>;
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def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, i32imm:$shcnt),
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!strconcat(OpcStr, " $rs1, $shcnt, $rd"),
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[(set VT:$rd, (OpNode VT:$rs1, (i32 imm:$shcnt)))],
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itin>;
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}
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class F4<bits<6> op3, dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin = NoItinerary>
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: InstSP<outs, ins, asmstr, pattern, itin> {
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bits<5> rd;
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let op = 2;
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let Inst{29-25} = rd;
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let Inst{24-19} = op3;
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}
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class F4_1<bits<6> op3, dag outs, dag ins,
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string asmstr, list<dag> pattern,
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InstrItinClass itin = NoItinerary>
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: F4<op3, outs, ins, asmstr, pattern, itin> {
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bit intcc;
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bits<2> cc;
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bits<4> cond;
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bits<5> rs2;
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let Inst{4-0} = rs2;
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let Inst{12-11} = cc;
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let Inst{13} = 0;
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let Inst{17-14} = cond;
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let Inst{18} = intcc;
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}
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class F4_2<bits<6> op3, dag outs, dag ins,
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string asmstr, list<dag> pattern,
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InstrItinClass itin = NoItinerary>
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: F4<op3, outs, ins, asmstr, pattern, itin> {
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bit intcc;
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bits<2> cc;
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bits<4> cond;
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bits<11> simm11;
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let Inst{10-0} = simm11;
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let Inst{12-11} = cc;
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let Inst{13} = 1;
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let Inst{17-14} = cond;
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let Inst{18} = intcc;
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}
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class F4_3<bits<6> op3, bits<6> opf_low, dag outs, dag ins,
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string asmstr, list<dag> pattern,
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InstrItinClass itin = NoItinerary>
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: F4<op3, outs, ins, asmstr, pattern, itin> {
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bits<4> cond;
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bit intcc;
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bits<2> opf_cc;
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bits<5> rs2;
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let Inst{18} = 0;
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let Inst{17-14} = cond;
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let Inst{13} = intcc;
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let Inst{12-11} = opf_cc;
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let Inst{10-5} = opf_low;
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let Inst{4-0} = rs2;
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}
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class F4_4r<bits<6> op3, bits<5> opf_low, bits<3> rcond, dag outs, dag ins,
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string asmstr, list<dag> pattern,
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InstrItinClass itin = NoItinerary>
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: F4<op3, outs, ins, asmstr, pattern, itin> {
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bits <5> rs1;
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bits <5> rs2;
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let Inst{18-14} = rs1;
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let Inst{13} = 0; // IsImm
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let Inst{12-10} = rcond;
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let Inst{9-5} = opf_low;
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let Inst{4-0} = rs2;
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}
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class F4_4i<bits<6> op3, bits<3> rcond, dag outs, dag ins,
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string asmstr, list<dag> pattern,
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InstrItinClass itin = NoItinerary>
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: F4<op3, outs, ins, asmstr, pattern, itin> {
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bits<5> rs1;
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bits<10> simm10;
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let Inst{18-14} = rs1;
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let Inst{13} = 1; // IsImm
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let Inst{12-10} = rcond;
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let Inst{9-0} = simm10;
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}
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class TRAPSP<bits<6> op3Val, bit isimm, dag outs, dag ins,
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string asmstr, list<dag> pattern,
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InstrItinClass itin = NoItinerary>
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: F3<outs, ins, asmstr, pattern, itin> {
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bits<4> cond;
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bits<2> cc;
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let op = 0b10;
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let rd{4} = 0;
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let rd{3-0} = cond;
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let op3 = op3Val;
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let Inst{13} = isimm;
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let Inst{12-11} = cc;
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}
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class TRAPSPrr<bits<6> op3Val, dag outs, dag ins,
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string asmstr, list<dag> pattern,
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InstrItinClass itin = NoItinerary>
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: TRAPSP<op3Val, 0, outs, ins, asmstr, pattern, itin> {
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bits<5> rs2;
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let Inst{10-5} = 0;
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let Inst{4-0} = rs2;
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}
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class TRAPSPri<bits<6> op3Val, dag outs, dag ins,
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string asmstr, list<dag> pattern,
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InstrItinClass itin = NoItinerary>
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: TRAPSP<op3Val, 1, outs, ins, asmstr, pattern, itin> {
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bits<8> imm;
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let Inst{10-8} = 0;
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let Inst{7-0} = imm;
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}
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// Pseudo-instructions for alternate assembly syntax (never used by codegen).
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// These are aliases that require C++ handling to convert to the target
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// instruction, while InstAliases can be handled directly by tblgen.
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class AsmPseudoInst<dag outs, dag ins, string asm>
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: InstSP<outs, ins, asm, []> {
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let isPseudo = 1;
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}
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