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52 lines
1.9 KiB
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52 lines
1.9 KiB
Plaintext
Date: Sun, 8 Jul 2001 09:37:22 -0500
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From: Vikram S. Adve <vadve@cs.uiuc.edu>
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To: Ruchira Sasanka <sasanka@students.uiuc.edu>
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Cc: Chris Lattner <lattner@cs.uiuc.edu>
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Subject: machine instruction operands
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Ruchira,
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When generating machine instructions, I have to make several choices about
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operands. For cases were a register is required, there are 3 cases:
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1. The register is for a Value* that is already in the VM code.
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2. The register is for a value that is not in the VM code, usually because 2
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machine instructions get generated for a single VM instruction (and the
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register holds the result of the first m/c instruction and is used by the
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second m/c instruction).
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3. The register is a pre-determined machine register.
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E.g, for this VM instruction:
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ptr = alloca type, numElements
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I have to generate 2 machine instructions:
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reg = mul constant, numElements
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ptr = add %sp, reg
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Each machine instruction is of class MachineInstr.
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It has a vector of operands. All register operands have type MO_REGISTER.
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The 3 types of register operands are marked using this enum:
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enum VirtualRegisterType {
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MO_VMVirtualReg, // virtual register for *value
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MO_MInstrVirtualReg, // virtual register for result of *minstr
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MO_MachineReg // pre-assigned machine register `regNum'
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} vregType;
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Here's how this affects register allocation:
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1. MO_VMVirtualReg is the standard case: you just do the register
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allocation.
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2. MO_MInstrVirtualReg is the case where there is a hidden register being
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used. You should decide how you want to handle it, e.g., do you want do
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create a Value object during the preprocessing phase to make the value
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explicit (like for address register for the RETURN instruction).
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3. For case MO_MachineReg, you don't need to do anything, at least for
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SPARC. The only machine regs I am using so far are %g0 and %sp.
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--Vikram
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