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https://github.com/RPCS3/llvm-mirror.git
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1e41909d2b
Add support for MIR serialization of PowerPC-specific operand target flags (based on the generic infrastructure added in r244185 and r245383). I won't even pretend that this is good test coverage, but this includes the regression test associated with r246372. Adding an MIR test for that fix is far superior to adding an IR-level test because particular instruction-scheduling decisions are necessary in order to expose the bug, and using an MIR test we can start the pipeline post-scheduling. llvm-svn: 246373
81 lines
3.1 KiB
YAML
81 lines
3.1 KiB
YAML
# RUN: llc -relocation-model=pic -start-after=block-placement -o - %s | FileCheck %s
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--- |
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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@x = internal thread_local unnamed_addr global i1 false
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@y = external thread_local global i32, align 4
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; Function Attrs: nounwind
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define void @test1() #0 {
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entry:
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store i1 true, i1* @x, align 1
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store i32 20, i32* @y, align 4
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ret void
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}
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attributes #0 = { nounwind "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "target-cpu"="pwr7" }
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!llvm.module.flags = !{!0}
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!0 = !{i32 1, !"PIC Level", i32 2}
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...
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---
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name: test1
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alignment: 4
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exposesReturnsTwice: false
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hasInlineAsm: false
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isSSA: false
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tracksRegLiveness: true
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tracksSubRegLiveness: false
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 64
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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maxCallFrameSize: 48
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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fixedStack:
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- { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%x30' }
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- { id: 1, offset: -8, size: 8, alignment: 8, isImmutable: true, isAliased: false }
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body: |
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bb.0.entry:
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liveins: %x30, %x30
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%x0 = MFLR8 implicit %lr8
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STD %x31, -8, %x1
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STD killed %x0, 16, %x1
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%x1 = STDU %x1, -64, %x1
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%x3 = ADDIStlsldHA %x2, @x
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%x31 = OR8 %x1, %x1
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%x3 = ADDItlsldL killed %x3, @x
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STD killed %x30, 48, %x31 :: (store 8 into %fixed-stack.0, align 16)
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%x3 = GETtlsldADDR killed %x3, @x, implicit-def dead %x0, implicit-def dead %x4, implicit-def dead %x5, implicit-def dead %x6, implicit-def dead %x7, implicit-def dead %x8, implicit-def dead %x9, implicit-def dead %x10, implicit-def dead %x11, implicit-def dead %x12, implicit-def %lr8, implicit-def %ctr8, implicit-def dead %cr0, implicit-def dead %cr1, implicit-def dead %cr5, implicit-def dead %cr6, implicit-def dead %cr7
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%x12 = ADDIStlsgdHA %x2, @y
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%x30 = OR8 killed %x3, %x3
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%x3 = ADDItlsgdL killed %x12, @y
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%x3 = GETtlsADDR killed %x3, @y, implicit-def dead %x0, implicit-def dead %x4, implicit-def dead %x5, implicit-def dead %x6, implicit-def dead %x7, implicit-def dead %x8, implicit-def dead %x9, implicit-def dead %x10, implicit-def dead %x11, implicit-def dead %x12, implicit-def %lr8, implicit-def %ctr8, implicit-def dead %cr0, implicit-def dead %cr1, implicit-def dead %cr5, implicit-def dead %cr6, implicit-def dead %cr7
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%x4 = ADDISdtprelHA killed %x30, @x
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; CHECK: addis 4, 30, x@dtprel@ha
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%x5 = LI8 1
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%r6 = LI 20
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%x30 = LD 48, %x31 :: (load 8 from %fixed-stack.0, align 16)
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STB8 killed %x5, target-flags(ppc-dtprel-lo) @x, killed %x4 :: (store 1 into @x)
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STW killed %r6, 0, killed %x3 :: (store 4 into @y)
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%x1 = ADDI8 %x1, 64
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%x0 = LD 16, %x1
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%x31 = LD -8, %x1
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MTLR8 killed %x0, implicit-def %lr8
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BLR8 implicit %lr8, implicit %rm
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...
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