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333 lines
14 KiB
TableGen
333 lines
14 KiB
TableGen
//===- HexagonImmediates.td - Hexagon immediate processing -*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illnois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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def s32_0ImmOperand : AsmOperandClass { let Name = "s32_0Imm"; }
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def s23_2ImmOperand : AsmOperandClass { let Name = "s23_2Imm"; }
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def s8_0ImmOperand : AsmOperandClass { let Name = "s8_0Imm"; }
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def s8_0Imm64Operand : AsmOperandClass { let Name = "s8_0Imm64"; }
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def s6_0ImmOperand : AsmOperandClass { let Name = "s6_0Imm"; }
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def s4_0ImmOperand : AsmOperandClass { let Name = "s4_0Imm"; }
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def s4_1ImmOperand : AsmOperandClass { let Name = "s4_1Imm"; }
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def s4_2ImmOperand : AsmOperandClass { let Name = "s4_2Imm"; }
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def s4_3ImmOperand : AsmOperandClass { let Name = "s4_3Imm"; }
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def s4_6ImmOperand : AsmOperandClass { let Name = "s4_6Imm"; }
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def s3_6ImmOperand : AsmOperandClass { let Name = "s3_6Imm"; }
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def u64_0ImmOperand : AsmOperandClass { let Name = "u64_0Imm"; }
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def u32_0ImmOperand : AsmOperandClass { let Name = "u32_0Imm"; }
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def u26_6ImmOperand : AsmOperandClass { let Name = "u26_6Imm"; }
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def u16_0ImmOperand : AsmOperandClass { let Name = "u16_0Imm"; }
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def u16_1ImmOperand : AsmOperandClass { let Name = "u16_1Imm"; }
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def u16_2ImmOperand : AsmOperandClass { let Name = "u16_2Imm"; }
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def u16_3ImmOperand : AsmOperandClass { let Name = "u16_3Imm"; }
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def u11_3ImmOperand : AsmOperandClass { let Name = "u11_3Imm"; }
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def u10_0ImmOperand : AsmOperandClass { let Name = "u10_0Imm"; }
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def u9_0ImmOperand : AsmOperandClass { let Name = "u9_0Imm"; }
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def u8_0ImmOperand : AsmOperandClass { let Name = "u8_0Imm"; }
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def u7_0ImmOperand : AsmOperandClass { let Name = "u7_0Imm"; }
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def u6_0ImmOperand : AsmOperandClass { let Name = "u6_0Imm"; }
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def u6_1ImmOperand : AsmOperandClass { let Name = "u6_1Imm"; }
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def u6_2ImmOperand : AsmOperandClass { let Name = "u6_2Imm"; }
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def u6_3ImmOperand : AsmOperandClass { let Name = "u6_3Imm"; }
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def u5_0ImmOperand : AsmOperandClass { let Name = "u5_0Imm"; }
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def u4_0ImmOperand : AsmOperandClass { let Name = "u4_0Imm"; }
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def u3_0ImmOperand : AsmOperandClass { let Name = "u3_0Imm"; }
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def u2_0ImmOperand : AsmOperandClass { let Name = "u2_0Imm"; }
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def u1_0ImmOperand : AsmOperandClass { let Name = "u1_0Imm"; }
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def n8_0ImmOperand : AsmOperandClass { let Name = "n8_0Imm"; }
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// Immediate operands.
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let OperandType = "OPERAND_IMMEDIATE",
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DecoderMethod = "unsignedImmDecoder" in {
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def s32_0Imm : Operand<i32> { let ParserMatchClass = s32_0ImmOperand;
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let DecoderMethod = "s32_0ImmDecoder"; }
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def s23_2Imm : Operand<i32> { let ParserMatchClass = s23_2ImmOperand; }
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def s8_0Imm : Operand<i32> { let ParserMatchClass = s8_0ImmOperand;
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let DecoderMethod = "s8_0ImmDecoder"; }
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def s8_0Imm64 : Operand<i64> { let ParserMatchClass = s8_0Imm64Operand;
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let DecoderMethod = "s8_0ImmDecoder"; }
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def s6_0Imm : Operand<i32> { let ParserMatchClass = s6_0ImmOperand;
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let DecoderMethod = "s6_0ImmDecoder"; }
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def s6_3Imm : Operand<i32>;
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def s4_0Imm : Operand<i32> { let ParserMatchClass = s4_0ImmOperand;
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let DecoderMethod = "s4_0ImmDecoder"; }
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def s4_1Imm : Operand<i32> { let ParserMatchClass = s4_1ImmOperand;
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let DecoderMethod = "s4_1ImmDecoder"; }
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def s4_2Imm : Operand<i32> { let ParserMatchClass = s4_2ImmOperand;
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let DecoderMethod = "s4_2ImmDecoder"; }
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def s4_3Imm : Operand<i32> { let ParserMatchClass = s4_3ImmOperand;
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let DecoderMethod = "s4_3ImmDecoder"; }
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def u64_0Imm : Operand<i64> { let ParserMatchClass = u64_0ImmOperand; }
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def u32_0Imm : Operand<i32> { let ParserMatchClass = u32_0ImmOperand; }
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def u26_6Imm : Operand<i32> { let ParserMatchClass = u26_6ImmOperand; }
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def u16_0Imm : Operand<i32> { let ParserMatchClass = u16_0ImmOperand; }
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def u16_1Imm : Operand<i32> { let ParserMatchClass = u16_1ImmOperand; }
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def u16_2Imm : Operand<i32> { let ParserMatchClass = u16_2ImmOperand; }
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def u16_3Imm : Operand<i32> { let ParserMatchClass = u16_3ImmOperand; }
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def u11_3Imm : Operand<i32> { let ParserMatchClass = u11_3ImmOperand; }
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def u10_0Imm : Operand<i32> { let ParserMatchClass = u10_0ImmOperand; }
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def u9_0Imm : Operand<i32> { let ParserMatchClass = u9_0ImmOperand; }
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def u8_0Imm : Operand<i32> { let ParserMatchClass = u8_0ImmOperand; }
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def u7_0Imm : Operand<i32> { let ParserMatchClass = u7_0ImmOperand; }
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def u6_0Imm : Operand<i32> { let ParserMatchClass = u6_0ImmOperand; }
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def u6_1Imm : Operand<i32> { let ParserMatchClass = u6_1ImmOperand; }
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def u6_2Imm : Operand<i32> { let ParserMatchClass = u6_2ImmOperand; }
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def u6_3Imm : Operand<i32> { let ParserMatchClass = u6_3ImmOperand; }
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def u5_0Imm : Operand<i32> { let ParserMatchClass = u5_0ImmOperand; }
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def u5_1Imm : Operand<i32>;
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def u5_2Imm : Operand<i32>;
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def u5_3Imm : Operand<i32>;
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def u4_0Imm : Operand<i32> { let ParserMatchClass = u4_0ImmOperand; }
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def u4_1Imm : Operand<i32>;
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def u4_2Imm : Operand<i32>;
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def u4_3Imm : Operand<i32>;
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def u3_0Imm : Operand<i32> { let ParserMatchClass = u3_0ImmOperand; }
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def u3_1Imm : Operand<i32>;
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def u3_2Imm : Operand<i32>;
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def u3_3Imm : Operand<i32>;
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def u2_0Imm : Operand<i32> { let ParserMatchClass = u2_0ImmOperand; }
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def u1_0Imm : Operand<i32> { let ParserMatchClass = u1_0ImmOperand; }
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def n8_0Imm : Operand<i32> { let ParserMatchClass = n8_0ImmOperand; }
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}
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let OperandType = "OPERAND_IMMEDIATE" in {
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def s4_6Imm : Operand<i32> { let ParserMatchClass = s4_6ImmOperand;
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let PrintMethod = "prints4_6ImmOperand";
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let DecoderMethod = "s4_6ImmDecoder";}
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def s4_7Imm : Operand<i32> { let PrintMethod = "prints4_7ImmOperand";
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let DecoderMethod = "s4_6ImmDecoder";}
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def s3_6Imm : Operand<i32> { let ParserMatchClass = s3_6ImmOperand;
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let PrintMethod = "prints3_6ImmOperand";
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let DecoderMethod = "s3_6ImmDecoder";}
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def s3_7Imm : Operand<i32> { let PrintMethod = "prints3_7ImmOperand";
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let DecoderMethod = "s3_6ImmDecoder";}
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}
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def n1ConstOperand : AsmOperandClass { let Name = "n1Const"; }
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def n1Const : Operand<i32> { let ParserMatchClass = n1ConstOperand; }
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//
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// Immediate predicates
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//
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def s32_0ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isInt<32>(v);
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}]>;
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def s31_1ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isShiftedInt<31,1>(v);
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}]>;
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def s30_2ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isShiftedInt<30,2>(v);
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}]>;
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def s29_3ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isShiftedInt<29,3>(v);
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}]>;
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def s10_0ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isInt<10>(v);
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}]>;
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def s8_0ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isInt<8>(v);
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}]>;
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def s8_0Imm64Pred : PatLeaf<(i64 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isInt<8>(v);
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}]>;
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def s6_0ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isInt<6>(v);
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}]>;
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def s4_0ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isInt<4>(v);
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}]>;
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def s4_1ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isShiftedInt<4,1>(v);
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}]>;
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def s4_2ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isShiftedInt<4,2>(v);
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}]>;
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def s4_3ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isShiftedInt<4,3>(v);
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}]>;
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def u32_0ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isUInt<32>(v);
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}]>;
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def u16_0ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isUInt<16>(v);
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}]>;
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def u11_3ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isShiftedUInt<11,3>(v);
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}]>;
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def u9_0ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isUInt<9>(v);
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}]>;
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def u8_0ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isUInt<8>(v);
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}]>;
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def u6_0ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isUInt<6>(v);
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}]>;
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def u6_1ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isShiftedUInt<6,1>(v);
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}]>;
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def u6_2ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isShiftedUInt<6,2>(v);
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}]>;
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def u5_0ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isUInt<5>(v);
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}]>;
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def u4_0ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isUInt<4>(v);
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}]>;
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def u3_0ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isUInt<3>(v);
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}]>;
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def u2_0ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isUInt<2>(v);
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}]>;
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// Extendable immediate operands.
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def f32ExtOperand : AsmOperandClass { let Name = "f32Ext"; }
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def s16_0ExtOperand : AsmOperandClass { let Name = "s16_0Ext"; }
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def s12_0ExtOperand : AsmOperandClass { let Name = "s12_0Ext"; }
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def s10_0ExtOperand : AsmOperandClass { let Name = "s10_0Ext"; }
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def s9_0ExtOperand : AsmOperandClass { let Name = "s9_0Ext"; }
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def s8_0ExtOperand : AsmOperandClass { let Name = "s8_0Ext"; }
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def s7_0ExtOperand : AsmOperandClass { let Name = "s7_0Ext"; }
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def s6_0ExtOperand : AsmOperandClass { let Name = "s6_0Ext"; }
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def s11_0ExtOperand : AsmOperandClass { let Name = "s11_0Ext"; }
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def s11_1ExtOperand : AsmOperandClass { let Name = "s11_1Ext"; }
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def s11_2ExtOperand : AsmOperandClass { let Name = "s11_2Ext"; }
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def s11_3ExtOperand : AsmOperandClass { let Name = "s11_3Ext"; }
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def u6_0ExtOperand : AsmOperandClass { let Name = "u6_0Ext"; }
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def u7_0ExtOperand : AsmOperandClass { let Name = "u7_0Ext"; }
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def u8_0ExtOperand : AsmOperandClass { let Name = "u8_0Ext"; }
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def u9_0ExtOperand : AsmOperandClass { let Name = "u9_0Ext"; }
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def u10_0ExtOperand : AsmOperandClass { let Name = "u10_0Ext"; }
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def u6_1ExtOperand : AsmOperandClass { let Name = "u6_1Ext"; }
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def u6_2ExtOperand : AsmOperandClass { let Name = "u6_2Ext"; }
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def u6_3ExtOperand : AsmOperandClass { let Name = "u6_3Ext"; }
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def u32_0MustExtOperand : AsmOperandClass { let Name = "u32_0MustExt"; }
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let OperandType = "OPERAND_IMMEDIATE", PrintMethod = "printExtOperand",
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DecoderMethod = "unsignedImmDecoder" in {
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def f32Ext : Operand<f32> { let ParserMatchClass = f32ExtOperand; }
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def s16_0Ext : Operand<i32> { let ParserMatchClass = s16_0ExtOperand;
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let DecoderMethod = "s16_0ImmDecoder"; }
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def s12_0Ext : Operand<i32> { let ParserMatchClass = s12_0ExtOperand;
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let DecoderMethod = "s12_0ImmDecoder"; }
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def s11_0Ext : Operand<i32> { let ParserMatchClass = s11_0ExtOperand;
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let DecoderMethod = "s11_0ImmDecoder"; }
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def s11_1Ext : Operand<i32> { let ParserMatchClass = s11_1ExtOperand;
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let DecoderMethod = "s11_1ImmDecoder"; }
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def s11_2Ext : Operand<i32> { let ParserMatchClass = s11_2ExtOperand;
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let DecoderMethod = "s11_2ImmDecoder"; }
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def s11_3Ext : Operand<i32> { let ParserMatchClass = s11_3ExtOperand;
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let DecoderMethod = "s11_3ImmDecoder"; }
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def s10_0Ext : Operand<i32> { let ParserMatchClass = s10_0ExtOperand;
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let DecoderMethod = "s10_0ImmDecoder"; }
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def s9_0Ext : Operand<i32> { let ParserMatchClass = s9_0ExtOperand;
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let DecoderMethod = "s9_0ImmDecoder"; }
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def s8_0Ext : Operand<i32> { let ParserMatchClass = s8_0ExtOperand;
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let DecoderMethod = "s8_0ImmDecoder"; }
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def s7_0Ext : Operand<i32> { let ParserMatchClass = s7_0ExtOperand; }
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def s6_0Ext : Operand<i32> { let ParserMatchClass = s6_0ExtOperand;
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let DecoderMethod = "s6_0ImmDecoder"; }
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def u7_0Ext : Operand<i32> { let ParserMatchClass = u7_0ExtOperand; }
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def u8_0Ext : Operand<i32> { let ParserMatchClass = u8_0ExtOperand; }
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def u9_0Ext : Operand<i32> { let ParserMatchClass = u9_0ExtOperand; }
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def u10_0Ext : Operand<i32> { let ParserMatchClass = u10_0ExtOperand; }
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def u6_0Ext : Operand<i32> { let ParserMatchClass = u6_0ExtOperand; }
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def u6_1Ext : Operand<i32> { let ParserMatchClass = u6_1ExtOperand; }
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def u6_2Ext : Operand<i32> { let ParserMatchClass = u6_2ExtOperand; }
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def u6_3Ext : Operand<i32> { let ParserMatchClass = u6_3ExtOperand; }
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def u32_0MustExt : Operand<i32> { let ParserMatchClass = u32_0MustExtOperand; }
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}
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// This complex pattern exists only to create a machine instruction operand
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// of type "frame index". There doesn't seem to be a way to do that directly
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// in the patterns.
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def AddrFI : ComplexPattern<i32, 1, "SelectAddrFI", [frameindex], []>;
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// These complex patterns are not strictly necessary, since global address
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// folding will happen during DAG combining. For distinguishing between GA
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// and GP, pat frags with HexagonCONST32 and HexagonCONST32_GP can be used.
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def AddrGA : ComplexPattern<i32, 1, "SelectAddrGA", [], []>;
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def AddrGP : ComplexPattern<i32, 1, "SelectAddrGP", [], []>;
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// Address operands.
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let PrintMethod = "printGlobalOperand" in {
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def globaladdress : Operand<i32>;
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def globaladdressExt : Operand<i32>;
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}
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let PrintMethod = "printJumpTable" in
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def jumptablebase : Operand<i32>;
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def brtarget : Operand<OtherVT> {
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let DecoderMethod = "brtargetDecoder";
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let PrintMethod = "printBrtarget";
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}
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def brtargetExt : Operand<OtherVT> {
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let DecoderMethod = "brtargetDecoder";
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let PrintMethod = "printBrtarget";
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}
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def calltarget : Operand<i32> {
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let DecoderMethod = "brtargetDecoder";
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let PrintMethod = "printBrtarget";
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}
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def bblabel : Operand<i32>;
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def bbl : SDNode<"ISD::BasicBlock", SDTPtrLeaf, [], "BasicBlockSDNode">;
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