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An encoding does not allow to use SDWA in an instruction with scalar operands, either literals or SGPRs. That is however possible to copy these operands into a VGPR first. Several copies of the value are produced if multiple SDWA conversions were done. To cleanup MachineLICM (to hoist copies out of loops), MachineCSE (to remove duplicate copies) and SIFoldOperands (to replace SGPR to VGPR copy with immediate copy right to the VGPR) runs are added after the SDWA pass. Differential Revision: https://reviews.llvm.org/D33583 llvm-svn: 304219
45 lines
1.8 KiB
LLVM
45 lines
1.8 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s
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; CHECK-LABEL: {{^}}v_fadd_f64:
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; CHECK: v_add_f64 {{v[[0-9]+:[0-9]+]}}, {{v[[0-9]+:[0-9]+]}}, {{v[[0-9]+:[0-9]+]}}
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define amdgpu_kernel void @v_fadd_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
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double addrspace(1)* %in2) {
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%r0 = load double, double addrspace(1)* %in1
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%r1 = load double, double addrspace(1)* %in2
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%r2 = fadd double %r0, %r1
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store double %r2, double addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}s_fadd_f64:
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; CHECK: v_add_f64 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @s_fadd_f64(double addrspace(1)* %out, double %r0, double %r1) {
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%r2 = fadd double %r0, %r1
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store double %r2, double addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}v_fadd_v2f64:
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; CHECK: v_add_f64
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; CHECK: v_add_f64
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; CHECK: _store_dwordx4
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define amdgpu_kernel void @v_fadd_v2f64(<2 x double> addrspace(1)* %out, <2 x double> addrspace(1)* %in1,
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<2 x double> addrspace(1)* %in2) {
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%r0 = load <2 x double>, <2 x double> addrspace(1)* %in1
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%r1 = load <2 x double>, <2 x double> addrspace(1)* %in2
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%r2 = fadd <2 x double> %r0, %r1
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store <2 x double> %r2, <2 x double> addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}s_fadd_v2f64:
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; CHECK: v_add_f64 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}
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; CHECK: v_add_f64 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}
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; CHECK: _store_dwordx4
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define amdgpu_kernel void @s_fadd_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %r0, <2 x double> %r1) {
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%r2 = fadd <2 x double> %r0, %r1
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store <2 x double> %r2, <2 x double> addrspace(1)* %out
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ret void
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}
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