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e23fa40f7f
An encoding does not allow to use SDWA in an instruction with scalar operands, either literals or SGPRs. That is however possible to copy these operands into a VGPR first. Several copies of the value are produced if multiple SDWA conversions were done. To cleanup MachineLICM (to hoist copies out of loops), MachineCSE (to remove duplicate copies) and SIFoldOperands (to replace SGPR to VGPR copy with immediate copy right to the VGPR) runs are added after the SDWA pass. Differential Revision: https://reviews.llvm.org/D33583 llvm-svn: 304219
102 lines
4.4 KiB
LLVM
102 lines
4.4 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s
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; FIXME: Check something here. Currently it seems fabs + fneg aren't
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; into 2 modifiers, although theoretically that should work.
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; GCN-LABEL: {{^}}fneg_fabs_fadd_f64:
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; GCN: v_add_f64 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, -|v{{\[[0-9]+:[0-9]+\]}}|
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define amdgpu_kernel void @fneg_fabs_fadd_f64(double addrspace(1)* %out, double %x, double %y) {
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%fabs = call double @llvm.fabs.f64(double %x)
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%fsub = fsub double -0.000000e+00, %fabs
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%fadd = fadd double %y, %fsub
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store double %fadd, double addrspace(1)* %out, align 8
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ret void
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}
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define amdgpu_kernel void @v_fneg_fabs_fadd_f64(double addrspace(1)* %out, double addrspace(1)* %xptr, double addrspace(1)* %yptr) {
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%x = load double, double addrspace(1)* %xptr, align 8
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%y = load double, double addrspace(1)* %xptr, align 8
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%fabs = call double @llvm.fabs.f64(double %x)
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%fsub = fsub double -0.000000e+00, %fabs
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%fadd = fadd double %y, %fsub
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store double %fadd, double addrspace(1)* %out, align 8
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ret void
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}
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; GCN-LABEL: {{^}}fneg_fabs_fmul_f64:
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; GCN: v_mul_f64 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, -|v{{\[[0-9]+:[0-9]+\]}}|
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define amdgpu_kernel void @fneg_fabs_fmul_f64(double addrspace(1)* %out, double %x, double %y) {
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%fabs = call double @llvm.fabs.f64(double %x)
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%fsub = fsub double -0.000000e+00, %fabs
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%fmul = fmul double %y, %fsub
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store double %fmul, double addrspace(1)* %out, align 8
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ret void
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}
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; GCN-LABEL: {{^}}fneg_fabs_free_f64:
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define amdgpu_kernel void @fneg_fabs_free_f64(double addrspace(1)* %out, i64 %in) {
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%bc = bitcast i64 %in to double
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%fabs = call double @llvm.fabs.f64(double %bc)
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%fsub = fsub double -0.000000e+00, %fabs
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store double %fsub, double addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}fneg_fabs_fn_free_f64:
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; GCN: v_bfrev_b32_e32 [[IMMREG:v[0-9]+]], 1{{$}}
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; GCN: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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define amdgpu_kernel void @fneg_fabs_fn_free_f64(double addrspace(1)* %out, i64 %in) {
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%bc = bitcast i64 %in to double
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%fabs = call double @fabs(double %bc)
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%fsub = fsub double -0.000000e+00, %fabs
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store double %fsub, double addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}fneg_fabs_f64:
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; GCN-DAG: s_load_dwordx2
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; GCN-DAG: v_bfrev_b32_e32 [[IMMREG:v[0-9]+]], 1{{$}}
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; SI-DAG: s_load_dwordx2 s{{\[}}[[LO_X:[0-9]+]]:[[HI_X:[0-9]+]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0xb
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; VI-DAG: s_load_dwordx2 s{{\[}}[[LO_X:[0-9]+]]:[[HI_X:[0-9]+]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0x2c
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; GCN-DAG: v_or_b32_e32 v[[HI_V:[0-9]+]], s[[HI_X]], [[IMMREG]]
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; GCN-DAG: v_mov_b32_e32 v[[LO_V:[0-9]+]], s[[LO_X]]
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; GCN: buffer_store_dwordx2 v{{\[}}[[LO_V]]:[[HI_V]]{{\]}}
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define amdgpu_kernel void @fneg_fabs_f64(double addrspace(1)* %out, double %in) {
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%fabs = call double @llvm.fabs.f64(double %in)
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%fsub = fsub double -0.000000e+00, %fabs
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store double %fsub, double addrspace(1)* %out, align 8
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ret void
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}
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; GCN-LABEL: {{^}}fneg_fabs_v2f64:
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; GCN: v_bfrev_b32_e32 [[IMMREG:v[0-9]+]], 1{{$}}
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; GCN-NOT: 0x80000000
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; GCN: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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; GCN: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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define amdgpu_kernel void @fneg_fabs_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %in) {
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%fabs = call <2 x double> @llvm.fabs.v2f64(<2 x double> %in)
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%fsub = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %fabs
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store <2 x double> %fsub, <2 x double> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}fneg_fabs_v4f64:
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; GCN: v_bfrev_b32_e32 [[IMMREG:v[0-9]+]], 1{{$}}
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; GCN-NOT: 0x80000000
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; GCN: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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; GCN: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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; GCN: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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; GCN: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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define amdgpu_kernel void @fneg_fabs_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %in) {
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%fabs = call <4 x double> @llvm.fabs.v4f64(<4 x double> %in)
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%fsub = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %fabs
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store <4 x double> %fsub, <4 x double> addrspace(1)* %out
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ret void
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}
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declare double @fabs(double) readnone
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declare double @llvm.fabs.f64(double) readnone
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declare <2 x double> @llvm.fabs.v2f64(<2 x double>) readnone
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declare <4 x double> @llvm.fabs.v4f64(<4 x double>) readnone
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