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0c1bf45146
Recently alloca address space has been added to data layout. Due to this change, pointer returned by alloca may have different size as pointer in address space 0. However, currently the value type of frame index is assumed to be of the same size as pointer in address space 0. This patch fixes that. Most targets assume alloca returning pointer in address space 0, which is the default alloca address space. Therefore it is NFC for them. AMDGCN target with amdgiz environment requires this change since it assumes alloca returning pointer to addr space 5 and its size is 32, which is different from the size of pointer in addr space 0 which is 64. Differential Revision: https://reviews.llvm.org/D32021 llvm-svn: 300864
56 lines
2.1 KiB
LLVM
56 lines
2.1 KiB
LLVM
; RUN: llc -verify-machineinstrs < %s | FileCheck %s
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;
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; The original OpenCL kernel:
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; kernel void f(global int *a, int i, int j) {
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; int x[100];
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; x[i] = 7;
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; a[0] = x[j];
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; }
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; clang -cc1 -triple amdgcn---amdgizcl -emit-llvm -o -
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target datalayout = "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"
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target triple = "amdgcn---amdgiz"
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define amdgpu_kernel void @f(i32 addrspace(1)* nocapture %a, i32 %i, i32 %j) local_unnamed_addr #0 {
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entry:
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; CHECK: s_load_dword s2, s[0:1], 0xb
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; CHECK: s_load_dwordx2 s[4:5], s[0:1], 0x9
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; CHECK: s_load_dword s0, s[0:1], 0xc
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; CHECK: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
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; CHECK: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
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; CHECK: s_mov_b32 s10, -1
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; CHECK: s_waitcnt lgkmcnt(0)
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; CHECK: s_lshl_b32 s1, s2, 2
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; CHECK: v_mov_b32_e32 v0, 4
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; CHECK: s_mov_b32 s11, 0xe8f000
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; CHECK: v_add_i32_e32 v1, vcc, s1, v0
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; CHECK: v_mov_b32_e32 v2, 7
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; CHECK: s_lshl_b32 s0, s0, 2
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; CHECK: buffer_store_dword v2, v1, s[8:11], s3 offen
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; CHECK: v_add_i32_e32 v0, vcc, s0, v0
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; CHECK: buffer_load_dword v0, v0, s[8:11], s3 offen
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; CHECK: s_mov_b32 s7, 0xf000
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; CHECK: s_mov_b32 s6, -1
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; CHECK: s_waitcnt vmcnt(0)
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; CHECK: buffer_store_dword v0, off, s[4:7], 0
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; CHECK: s_endpgm
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%x = alloca [100 x i32], align 4, addrspace(5)
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%0 = bitcast [100 x i32] addrspace(5)* %x to i8 addrspace(5)*
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call void @llvm.lifetime.start.p5i8(i64 400, i8 addrspace(5)* nonnull %0) #0
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%arrayidx = getelementptr inbounds [100 x i32], [100 x i32] addrspace(5)* %x, i32 0, i32 %i
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store i32 7, i32 addrspace(5)* %arrayidx, align 4
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%arrayidx2 = getelementptr inbounds [100 x i32], [100 x i32] addrspace(5)* %x, i32 0, i32 %j
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%1 = load i32, i32 addrspace(5)* %arrayidx2, align 4
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store i32 %1, i32 addrspace(1)* %a, align 4
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call void @llvm.lifetime.end.p5i8(i64 400, i8 addrspace(5)* nonnull %0) #0
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ret void
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}
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declare void @llvm.lifetime.start.p5i8(i64, i8 addrspace(5)* nocapture) #1
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declare void @llvm.lifetime.end.p5i8(i64, i8 addrspace(5)* nocapture) #1
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attributes #0 = { nounwind }
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attributes #1 = { argmemonly nounwind }
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