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llvm-mirror/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.vol.ll
Mark Searles ecdf6429da [AMDGPU] Turn on the new waitcnt insertion pass. Adjust tests.
-enable-si-insert-waitcnts=1 becomes the default
-enable-si-insert-waitcnts=0 to use old pass

Differential Revision: https://reviews.llvm.org/D33730

llvm-svn: 304551
2017-06-02 14:19:25 +00:00

30 lines
857 B
LLVM

; RUN: llc -march=amdgcn -mcpu=fiji -show-mc-encoding < %s | FileCheck -check-prefix=VI %s
declare void @llvm.amdgcn.s.dcache.wb.vol() #0
declare void @llvm.amdgcn.s.waitcnt(i32) #0
; VI-LABEL: {{^}}test_s_dcache_wb_vol:
; VI-NEXT: ; BB#0:
; VI-NEXT: s_dcache_wb_vol ; encoding: [0x00,0x00,0x8c,0xc0,0x00,0x00,0x00,0x00]
; VI-NEXT: s_endpgm
define amdgpu_kernel void @test_s_dcache_wb_vol() #0 {
call void @llvm.amdgcn.s.dcache.wb.vol()
ret void
}
; VI-LABEL: {{^}}test_s_dcache_wb_vol_insert_wait:
; VI-NEXT: ; BB#0:
; VI-NEXT: s_dcache_wb_vol
; VI: s_waitcnt lgkmcnt(0) ; encoding
define amdgpu_kernel void @test_s_dcache_wb_vol_insert_wait() #0 {
call void @llvm.amdgcn.s.dcache.wb.vol()
call void @llvm.amdgcn.s.waitcnt(i32 127)
br label %end
end:
store volatile i32 3, i32 addrspace(1)* undef
ret void
}
attributes #0 = { nounwind }