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e23fa40f7f
An encoding does not allow to use SDWA in an instruction with scalar operands, either literals or SGPRs. That is however possible to copy these operands into a VGPR first. Several copies of the value are produced if multiple SDWA conversions were done. To cleanup MachineLICM (to hoist copies out of loops), MachineCSE (to remove duplicate copies) and SIFoldOperands (to replace SGPR to VGPR copy with immediate copy right to the VGPR) runs are added after the SDWA pass. Differential Revision: https://reviews.llvm.org/D33583 llvm-svn: 304219
172 lines
6.3 KiB
LLVM
172 lines
6.3 KiB
LLVM
; RUN: llc -march=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; The code generated by sdiv is long and complex and may frequently change.
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; The goal of this test is to make sure the ISel doesn't fail.
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;
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; This program was previously failing to compile when one of the selectcc
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; opcodes generated by the sdiv lowering was being legalized and optimized to:
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; selectcc Remainder -1, 0, -1, SETGT
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; This was fixed by adding an additional pattern in R600Instructions.td to
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; match this pattern with a CNDGE_INT.
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; FUNC-LABEL: {{^}}sdiv_i32:
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; EG: CF_END
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define amdgpu_kernel void @sdiv_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
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%num = load i32, i32 addrspace(1) * %in
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%den = load i32, i32 addrspace(1) * %den_ptr
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%result = sdiv i32 %num, %den
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}sdiv_i32_4:
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define amdgpu_kernel void @sdiv_i32_4(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%num = load i32, i32 addrspace(1) * %in
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%result = sdiv i32 %num, 4
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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; Multiply by a weird constant to make sure setIntDivIsCheap is
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; working.
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; FUNC-LABEL: {{^}}slow_sdiv_i32_3435:
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; SI-DAG: buffer_load_dword [[VAL:v[0-9]+]],
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; SI-DAG: v_mov_b32_e32 [[MAGIC:v[0-9]+]], 0x98a1930b
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; SI: v_mul_hi_i32 [[TMP:v[0-9]+]], [[VAL]], [[MAGIC]]
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; SI: v_add_i32
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; SI: v_lshrrev_b32
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; SI: v_ashrrev_i32
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; SI: v_add_i32
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; SI: buffer_store_dword
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; SI: s_endpgm
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define amdgpu_kernel void @slow_sdiv_i32_3435(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%num = load i32, i32 addrspace(1) * %in
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%result = sdiv i32 %num, 3435
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @sdiv_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
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%den_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
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%num = load <2 x i32>, <2 x i32> addrspace(1) * %in
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%den = load <2 x i32>, <2 x i32> addrspace(1) * %den_ptr
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%result = sdiv <2 x i32> %num, %den
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store <2 x i32> %result, <2 x i32> addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @sdiv_v2i32_4(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
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%num = load <2 x i32>, <2 x i32> addrspace(1) * %in
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%result = sdiv <2 x i32> %num, <i32 4, i32 4>
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store <2 x i32> %result, <2 x i32> addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @sdiv_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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%den_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
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%num = load <4 x i32>, <4 x i32> addrspace(1) * %in
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%den = load <4 x i32>, <4 x i32> addrspace(1) * %den_ptr
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%result = sdiv <4 x i32> %num, %den
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store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @sdiv_v4i32_4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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%num = load <4 x i32>, <4 x i32> addrspace(1) * %in
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%result = sdiv <4 x i32> %num, <i32 4, i32 4, i32 4, i32 4>
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store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}v_sdiv_i8:
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; SI: v_rcp_f32
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; SI: v_bfe_i32 [[BFE:v[0-9]+]], v{{[0-9]+}}, 0, 8
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; SI: buffer_store_dword [[BFE]]
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define amdgpu_kernel void @v_sdiv_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) {
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%den_ptr = getelementptr i8, i8 addrspace(1)* %in, i8 1
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%num = load i8, i8 addrspace(1) * %in
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%den = load i8, i8 addrspace(1) * %den_ptr
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%result = sdiv i8 %num, %den
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%result.ext = sext i8 %result to i32
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store i32 %result.ext, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}v_sdiv_i23:
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; SI: v_rcp_f32
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; SI: v_bfe_i32 [[BFE:v[0-9]+]], v{{[0-9]+}}, 0, 23
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; SI: buffer_store_dword [[BFE]]
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define amdgpu_kernel void @v_sdiv_i23(i32 addrspace(1)* %out, i23 addrspace(1)* %in) {
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%den_ptr = getelementptr i23, i23 addrspace(1)* %in, i23 1
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%num = load i23, i23 addrspace(1) * %in
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%den = load i23, i23 addrspace(1) * %den_ptr
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%result = sdiv i23 %num, %den
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%result.ext = sext i23 %result to i32
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store i32 %result.ext, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}v_sdiv_i24:
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; SI: v_rcp_f32
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; SI: v_bfe_i32 [[BFE:v[0-9]+]], v{{[0-9]+}}, 0, 24
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; SI: buffer_store_dword [[BFE]]
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define amdgpu_kernel void @v_sdiv_i24(i32 addrspace(1)* %out, i24 addrspace(1)* %in) {
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%den_ptr = getelementptr i24, i24 addrspace(1)* %in, i24 1
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%num = load i24, i24 addrspace(1) * %in
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%den = load i24, i24 addrspace(1) * %den_ptr
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%result = sdiv i24 %num, %den
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%result.ext = sext i24 %result to i32
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store i32 %result.ext, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}v_sdiv_i25:
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; SI-NOT: v_rcp_f32
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define amdgpu_kernel void @v_sdiv_i25(i32 addrspace(1)* %out, i25 addrspace(1)* %in) {
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%den_ptr = getelementptr i25, i25 addrspace(1)* %in, i25 1
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%num = load i25, i25 addrspace(1) * %in
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%den = load i25, i25 addrspace(1) * %den_ptr
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%result = sdiv i25 %num, %den
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%result.ext = sext i25 %result to i32
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store i32 %result.ext, i32 addrspace(1)* %out
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ret void
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}
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; Tests for 64-bit divide bypass.
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; define amdgpu_kernel void @test_get_quotient(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
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; %result = sdiv i64 %a, %b
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; store i64 %result, i64 addrspace(1)* %out, align 8
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; ret void
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; }
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; define amdgpu_kernel void @test_get_remainder(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
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; %result = srem i64 %a, %b
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; store i64 %result, i64 addrspace(1)* %out, align 8
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; ret void
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; }
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; define amdgpu_kernel void @test_get_quotient_and_remainder(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
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; %resultdiv = sdiv i64 %a, %b
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; %resultrem = srem i64 %a, %b
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; %result = add i64 %resultdiv, %resultrem
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; store i64 %result, i64 addrspace(1)* %out, align 8
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; ret void
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; }
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; FUNC-LABEL: @scalarize_mulhs_4xi32
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; SI: v_mul_hi_i32
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; SI: v_mul_hi_i32
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; SI: v_mul_hi_i32
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; SI: v_mul_hi_i32
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define amdgpu_kernel void @scalarize_mulhs_4xi32(<4 x i32> addrspace(1)* nocapture readonly %in, <4 x i32> addrspace(1)* nocapture %out) {
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%1 = load <4 x i32>, <4 x i32> addrspace(1)* %in, align 16
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%2 = sdiv <4 x i32> %1, <i32 53668, i32 53668, i32 53668, i32 53668>
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store <4 x i32> %2, <4 x i32> addrspace(1)* %out, align 16
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ret void
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}
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