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7555ade6d7
-mvzeroupper will force the vzeroupper insertion pass to run on CPUs that normally wouldn't. -mno-vzeroupper disables it on CPUs where it normally runs. To support this with the default feature handling in clang, we need a vzeroupper feature flag in X86.td. Since this flag has the opposite polarity of the fast-partial-ymm-or-zmm-write we used to use to disable the pass, we now need to add this new flag to every CPU except KNL/KNM and BTVER2 to keep identical behavior. Remove -fast-partial-ymm-or-zmm-write which is no longer used. Differential Revision: https://reviews.llvm.org/D69786
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=========================
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LLVM 10.0.0 Release Notes
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=========================
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.. contents::
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:local:
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.. warning::
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These are in-progress notes for the upcoming LLVM 10 release.
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Release notes for previous releases can be found on
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`the Download Page <https://releases.llvm.org/download.html>`_.
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Introduction
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============
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This document contains the release notes for the LLVM Compiler Infrastructure,
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release 10.0.0. Here we describe the status of LLVM, including major improvements
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from the previous release, improvements in various subprojects of LLVM, and
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some of the current users of the code. All LLVM releases may be downloaded
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from the `LLVM releases web site <https://llvm.org/releases/>`_.
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For more information about LLVM, including information about the latest
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release, please check out the `main LLVM web site <https://llvm.org/>`_. If you
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have questions or comments, the `LLVM Developer's Mailing List
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<https://lists.llvm.org/mailman/listinfo/llvm-dev>`_ is a good place to send
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them.
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Note that if you are reading this file from a Subversion checkout or the main
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LLVM web page, this document applies to the *next* release, not the current
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one. To see the release notes for a specific release, please see the `releases
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page <https://llvm.org/releases/>`_.
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Non-comprehensive list of changes in this release
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=================================================
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.. NOTE
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For small 1-3 sentence descriptions, just add an entry at the end of
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this list. If your description won't fit comfortably in one bullet
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point (e.g. maybe you would like to give an example of the
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functionality, or simply have a lot to talk about), see the `NOTE` below
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for adding a new subsection.
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* The ISD::FP_ROUND_INREG opcode and related code was removed from SelectionDAG.
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* Enabled MemorySSA as a loop dependency. Since
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`r370957 <https://reviews.llvm.org/rL370957>`_
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(`D58311 <https://reviews.llvm.org/D58311>`_ ``[MemorySSA & LoopPassManager]
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Enable MemorySSA as loop dependency. Update tests.``), the MemorySSA analysis
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is being preserved and used by a series of loop passes. The most significant
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use is in LICM, where the instruction hoisting and sinking relies on aliasing
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information provided by MemorySSA vs previously creating an AliasSetTracker.
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The LICM step of promoting variables to scalars still relies on the creation
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of an AliasSetTracker, but its use is reduced to only be enabled for loops
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with a small number of overall memory instructions. This choice was motivated
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by experimental results showing compile and run time benefits or replacing the
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AliasSetTracker usage with MemorySSA without any performance penalties.
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The fact that MemorySSA is now preserved by and available in a series of loop
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passes, also opens up opportunities for its use in those respective passes.
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* The BasicBlockPass, BBPassManager and all their uses were deleted in
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`this revision <https://reviews.llvm.org/rG9f0ff0b2634bab6a5be8dace005c9eb24d386dd1>`_.
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.. NOTE
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If you would like to document a larger change, then you can add a
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subsection about it right here. You can copy the following boilerplate
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and un-indent it (the indentation causes it to be inside this comment).
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Special New Feature
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-------------------
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Makes programs 10x faster by doing Special New Thing.
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* As per :ref:`LLVM Language Reference Manual <i_getelementptr>`,
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``getelementptr inbounds`` can not change the null status of a pointer,
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meaning it can not produce non-null pointer given null base pointer, and
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likewise given non-null base pointer it can not produce null pointer; if it
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does, the result is a :ref:`poison value <poisonvalues>`.
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Since `r369789 <https://reviews.llvm.org/rL369789>`_
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(`D66608 <https://reviews.llvm.org/D66608>`_ ``[InstCombine] icmp eq/ne (gep
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inbounds P, Idx..), null -> icmp eq/ne P, null``) LLVM uses that for
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transformations. If the original source violates these requirements this
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may result in code being miscompiled. If you are using Clang front-end,
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Undefined Behaviour Sanitizer ``-fsanitize=pointer-overflow`` check
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will now catch such cases.
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* Windows Control Flow Guard: the ``-cfguard`` option now emits CFG checks on
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indirect function calls. The previous behavior is still available with the
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``-cfguard-nochecks`` option. Note that this feature should always be used
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with optimizations enabled.
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Changes to the LLVM IR
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----------------------
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* Unnamed function arguments now get printed with their automatically
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generated name (e.g. "i32 %0") in definitions. This may require front-ends
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to update their tests; if so there is a script utils/add_argument_names.py
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that correctly converted 80-90% of Clang tests. Some manual work will almost
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certainly still be needed.
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Changes to building LLVM
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------------------------
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Changes to the ARM Backend
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--------------------------
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During this release ...
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Changes to the MIPS Target
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--------------------------
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During this release ...
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Changes to the PowerPC Target
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-----------------------------
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During this release ...
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Changes to the X86 Target
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-------------------------
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During this release ...
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* Less than 128 bit vector types, v2i32, v4i16, v2i16, v8i8, v4i8, and v2i8, are
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now stored in the lower bits of an xmm register and the upper bits are
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undefined. Previously the elements were spread apart with undefined bits in
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between them.
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* v32i8 and v64i8 vectors with AVX512F enabled, but AVX512BW disabled will now
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be passed in ZMM registers for calls and returns. Previously they were passed
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in two YMM registers. Old behavior can be enabled by passing
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-x86-enable-old-knl-abi
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* -mprefer-vector-width=256 is now the default behavior skylake-avx512 and later
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Intel CPUs. This tries to limit the use of 512-bit registers which can cause a
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decrease in CPU frequency on these CPUs. This can be re-enabled by passing
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-mprefer-vector-width=512 to clang or passing -mattr=-prefer-256-bit to llc.
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* Deprecated the mpx feature flag for the Intel MPX instructions. There were no
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intrinsics for this feature. This change only this effects the results
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returned by getHostCPUFeatures on CPUs that implement the MPX instructions.
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* The feature flag fast-partial-ymm-or-zmm-write which previously disabled
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vzeroupper insertion has been removed. It has been replaced with a vzeroupper
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feature flag which has the opposite polarity. So -vzeroupper has the same
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effect as +fast-partial-ymm-or-zmm-write.
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Changes to the AMDGPU Target
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-----------------------------
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Changes to the AVR Target
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-----------------------------
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During this release ...
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Changes to the WebAssembly Target
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---------------------------------
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During this release ...
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Changes to the OCaml bindings
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-----------------------------
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Changes to the C API
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--------------------
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Changes to the DAG infrastructure
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---------------------------------
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Changes to LLDB
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===============
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External Open Source Projects Using LLVM 10
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===========================================
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* A project...
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Additional Information
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======================
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A wide variety of additional information is available on the `LLVM web page
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<https://llvm.org/>`_, in particular in the `documentation
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<https://llvm.org/docs/>`_ section. The web page also contains versions of the
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API documentation which is up-to-date with the Subversion version of the source
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code. You can access versions of these documents specific to this release by
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going into the ``llvm/docs/`` directory in the LLVM tree.
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If you have any questions or comments about LLVM, please feel free to contact
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us via the `mailing lists <https://llvm.org/docs/#mailing-lists>`_.
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