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9260748488
AMDGPU target run out of Subtarget feature flags hitting the limit of 64. AssemblerPredicates uses at most uint64_t for their representation. At the same time CodeGen has exhausted this a long time ago and switched to a FeatureBitset with the current limit of 192 bits. This patch completes transition to the bitset for feature bits extending it to asm matcher and MC code emitter. Differential Revision: https://reviews.llvm.org/D59002 llvm-svn: 355839
94 lines
3.3 KiB
C++
94 lines
3.3 KiB
C++
//===- HexagonMCCodeEmitter.h - Hexagon Target Descriptions -----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// Definition for classes that emit Hexagon machine code from MCInsts
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCCODEEMITTER_H
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#define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCCODEEMITTER_H
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#include "MCTargetDesc/HexagonFixupKinds.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/SubtargetFeature.h"
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#include <cstddef>
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#include <cstdint>
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#include <memory>
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namespace llvm {
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class MCContext;
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class MCInst;
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class MCInstrInfo;
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class MCOperand;
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class MCSubtargetInfo;
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class raw_ostream;
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class HexagonMCCodeEmitter : public MCCodeEmitter {
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MCContext &MCT;
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MCInstrInfo const &MCII;
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// A mutable state of the emitter when encoding bundles and duplexes.
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struct EmitterState {
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unsigned Addend = 0;
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bool Extended = false;
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bool SubInst1 = false;
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const MCInst *Bundle = nullptr;
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size_t Index = 0;
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};
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mutable EmitterState State;
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public:
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HexagonMCCodeEmitter(MCInstrInfo const &MII, MCContext &MCT)
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: MCT(MCT), MCII(MII) {}
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void encodeInstruction(MCInst const &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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MCSubtargetInfo const &STI) const override;
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void EncodeSingleInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI,
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uint32_t Parse) const;
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// TableGen'erated function for getting the
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// binary encoding for an instruction.
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uint64_t getBinaryCodeForInstr(MCInst const &MI,
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SmallVectorImpl<MCFixup> &Fixups,
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MCSubtargetInfo const &STI) const;
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/// Return binary encoding of operand.
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unsigned getMachineOpValue(MCInst const &MI, MCOperand const &MO,
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SmallVectorImpl<MCFixup> &Fixups,
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MCSubtargetInfo const &STI) const;
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private:
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// helper routine for getMachineOpValue()
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unsigned getExprOpValue(const MCInst &MI, const MCOperand &MO,
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const MCExpr *ME, SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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Hexagon::Fixups getFixupNoBits(MCInstrInfo const &MCII, const MCInst &MI,
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const MCOperand &MO,
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const MCSymbolRefExpr::VariantKind Kind) const;
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// Return parse bits for instruction `MCI' inside bundle `MCB'
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uint32_t parseBits(size_t Last, MCInst const &MCB, MCInst const &MCI) const;
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FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) const;
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void
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verifyInstructionPredicates(const MCInst &MI,
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const FeatureBitset &AvailableFeatures) const;
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCCODEEMITTER_H
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