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0d78943f2c
Change the interface of CallLowering::lowerCall to accept several virtual registers for the call result, instead of just one. This is a follow-up to D46018. CallLowering::lowerReturn was similarly refactored in D49660 and lowerFormalArguments in D63549. With this change, we no longer pack the virtual registers generated for aggregates into one big lump before delegating to the target. Therefore, the target can decide itself whether it wants to handle them as separate pieces or use one big register. ARM and AArch64 have been updated to use the passed in virtual registers directly, which means we no longer need to generate so many merge/extract instructions. NFCI for AMDGPU, Mips and X86. Differential Revision: https://reviews.llvm.org/D63550 llvm-svn: 364511
472 lines
19 KiB
C++
472 lines
19 KiB
C++
//===- ARMLegalizerInfo.cpp --------------------------------------*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the targeting of the Machinelegalizer class for ARM.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#include "ARMLegalizerInfo.h"
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#include "ARMCallLowering.h"
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#include "ARMSubtarget.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
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#include "llvm/CodeGen/LowLevelType.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetOpcodes.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/Type.h"
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using namespace llvm;
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using namespace LegalizeActions;
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/// FIXME: The following static functions are SizeChangeStrategy functions
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/// that are meant to temporarily mimic the behaviour of the old legalization
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/// based on doubling/halving non-legal types as closely as possible. This is
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/// not entirly possible as only legalizing the types that are exactly a power
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/// of 2 times the size of the legal types would require specifying all those
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/// sizes explicitly.
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/// In practice, not specifying those isn't a problem, and the below functions
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/// should disappear quickly as we add support for legalizing non-power-of-2
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/// sized types further.
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static void
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addAndInterleaveWithUnsupported(LegalizerInfo::SizeAndActionsVec &result,
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const LegalizerInfo::SizeAndActionsVec &v) {
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for (unsigned i = 0; i < v.size(); ++i) {
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result.push_back(v[i]);
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if (i + 1 < v[i].first && i + 1 < v.size() &&
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v[i + 1].first != v[i].first + 1)
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result.push_back({v[i].first + 1, Unsupported});
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}
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}
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static LegalizerInfo::SizeAndActionsVec
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widen_8_16(const LegalizerInfo::SizeAndActionsVec &v) {
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assert(v.size() >= 1);
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assert(v[0].first > 17);
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LegalizerInfo::SizeAndActionsVec result = {{1, Unsupported},
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{8, WidenScalar},
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{9, Unsupported},
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{16, WidenScalar},
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{17, Unsupported}};
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addAndInterleaveWithUnsupported(result, v);
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auto Largest = result.back().first;
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result.push_back({Largest + 1, Unsupported});
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return result;
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}
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static bool AEABI(const ARMSubtarget &ST) {
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return ST.isTargetAEABI() || ST.isTargetGNUAEABI() || ST.isTargetMuslAEABI();
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}
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ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
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using namespace TargetOpcode;
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const LLT p0 = LLT::pointer(0, 32);
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const LLT s1 = LLT::scalar(1);
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const LLT s8 = LLT::scalar(8);
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const LLT s16 = LLT::scalar(16);
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const LLT s32 = LLT::scalar(32);
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const LLT s64 = LLT::scalar(64);
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if (ST.isThumb1Only()) {
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// Thumb1 is not supported yet.
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computeTables();
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verify(*ST.getInstrInfo());
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return;
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}
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getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT})
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.legalForCartesianProduct({s8, s16, s32}, {s1, s8, s16});
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getActionDefinitionsBuilder({G_MUL, G_AND, G_OR, G_XOR})
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.legalFor({s32})
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.minScalar(0, s32);
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if (ST.hasNEON())
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getActionDefinitionsBuilder({G_ADD, G_SUB})
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.legalFor({s32, s64})
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.minScalar(0, s32);
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else
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getActionDefinitionsBuilder({G_ADD, G_SUB})
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.legalFor({s32})
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.minScalar(0, s32);
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getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL})
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.legalFor({{s32, s32}})
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.minScalar(0, s32)
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.clampScalar(1, s32, s32);
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bool HasHWDivide = (!ST.isThumb() && ST.hasDivideInARMMode()) ||
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(ST.isThumb() && ST.hasDivideInThumbMode());
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if (HasHWDivide)
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getActionDefinitionsBuilder({G_SDIV, G_UDIV})
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.legalFor({s32})
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.clampScalar(0, s32, s32);
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else
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getActionDefinitionsBuilder({G_SDIV, G_UDIV})
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.libcallFor({s32})
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.clampScalar(0, s32, s32);
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for (unsigned Op : {G_SREM, G_UREM}) {
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setLegalizeScalarToDifferentSizeStrategy(Op, 0, widen_8_16);
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if (HasHWDivide)
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setAction({Op, s32}, Lower);
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else if (AEABI(ST))
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setAction({Op, s32}, Custom);
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else
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setAction({Op, s32}, Libcall);
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}
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getActionDefinitionsBuilder(G_INTTOPTR)
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.legalFor({{p0, s32}})
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.minScalar(1, s32);
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getActionDefinitionsBuilder(G_PTRTOINT)
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.legalFor({{s32, p0}})
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.minScalar(0, s32);
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getActionDefinitionsBuilder(G_CONSTANT)
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.legalFor({s32, p0})
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.clampScalar(0, s32, s32);
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getActionDefinitionsBuilder(G_ICMP)
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.legalForCartesianProduct({s1}, {s32, p0})
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.minScalar(1, s32);
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getActionDefinitionsBuilder(G_SELECT)
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.legalForCartesianProduct({s32, p0}, {s1})
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.minScalar(0, s32);
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// We're keeping these builders around because we'll want to add support for
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// floating point to them.
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auto &LoadStoreBuilder = getActionDefinitionsBuilder({G_LOAD, G_STORE})
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.legalForTypesWithMemDesc({{s1, p0, 8, 8},
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{s8, p0, 8, 8},
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{s16, p0, 16, 8},
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{s32, p0, 32, 8},
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{p0, p0, 32, 8}})
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.unsupportedIfMemSizeNotPow2();
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getActionDefinitionsBuilder(G_FRAME_INDEX).legalFor({p0});
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getActionDefinitionsBuilder(G_GLOBAL_VALUE).legalFor({p0});
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auto &PhiBuilder =
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getActionDefinitionsBuilder(G_PHI)
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.legalFor({s32, p0})
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.minScalar(0, s32);
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getActionDefinitionsBuilder(G_GEP)
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.legalFor({{p0, s32}})
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.minScalar(1, s32);
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getActionDefinitionsBuilder(G_BRCOND).legalFor({s1});
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if (!ST.useSoftFloat() && ST.hasVFP2Base()) {
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getActionDefinitionsBuilder(
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{G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FCONSTANT, G_FNEG})
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.legalFor({s32, s64});
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LoadStoreBuilder
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.legalForTypesWithMemDesc({{s64, p0, 64, 32}})
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.maxScalar(0, s32);
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PhiBuilder.legalFor({s64});
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getActionDefinitionsBuilder(G_FCMP).legalForCartesianProduct({s1},
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{s32, s64});
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getActionDefinitionsBuilder(G_MERGE_VALUES).legalFor({{s64, s32}});
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getActionDefinitionsBuilder(G_UNMERGE_VALUES).legalFor({{s32, s64}});
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getActionDefinitionsBuilder(G_FPEXT).legalFor({{s64, s32}});
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getActionDefinitionsBuilder(G_FPTRUNC).legalFor({{s32, s64}});
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getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
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.legalForCartesianProduct({s32}, {s32, s64});
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getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
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.legalForCartesianProduct({s32, s64}, {s32});
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} else {
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getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV})
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.libcallFor({s32, s64});
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LoadStoreBuilder.maxScalar(0, s32);
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for (auto Ty : {s32, s64})
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setAction({G_FNEG, Ty}, Lower);
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getActionDefinitionsBuilder(G_FCONSTANT).customFor({s32, s64});
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getActionDefinitionsBuilder(G_FCMP).customForCartesianProduct({s1},
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{s32, s64});
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if (AEABI(ST))
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setFCmpLibcallsAEABI();
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else
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setFCmpLibcallsGNU();
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getActionDefinitionsBuilder(G_FPEXT).libcallFor({{s64, s32}});
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getActionDefinitionsBuilder(G_FPTRUNC).libcallFor({{s32, s64}});
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getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
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.libcallForCartesianProduct({s32}, {s32, s64});
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getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
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.libcallForCartesianProduct({s32, s64}, {s32});
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}
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if (!ST.useSoftFloat() && ST.hasVFP4Base())
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getActionDefinitionsBuilder(G_FMA).legalFor({s32, s64});
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else
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getActionDefinitionsBuilder(G_FMA).libcallFor({s32, s64});
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getActionDefinitionsBuilder({G_FREM, G_FPOW}).libcallFor({s32, s64});
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if (ST.hasV5TOps()) {
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getActionDefinitionsBuilder(G_CTLZ)
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.legalFor({s32, s32})
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.clampScalar(1, s32, s32)
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.clampScalar(0, s32, s32);
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getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF)
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.lowerFor({s32, s32})
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.clampScalar(1, s32, s32)
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.clampScalar(0, s32, s32);
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} else {
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getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF)
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.libcallFor({s32, s32})
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.clampScalar(1, s32, s32)
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.clampScalar(0, s32, s32);
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getActionDefinitionsBuilder(G_CTLZ)
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.lowerFor({s32, s32})
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.clampScalar(1, s32, s32)
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.clampScalar(0, s32, s32);
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}
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computeTables();
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verify(*ST.getInstrInfo());
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}
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void ARMLegalizerInfo::setFCmpLibcallsAEABI() {
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// FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be
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// default-initialized.
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FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
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FCmp32Libcalls[CmpInst::FCMP_OEQ] = {
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{RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE}};
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FCmp32Libcalls[CmpInst::FCMP_OGE] = {
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{RTLIB::OGE_F32, CmpInst::BAD_ICMP_PREDICATE}};
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FCmp32Libcalls[CmpInst::FCMP_OGT] = {
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{RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE}};
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FCmp32Libcalls[CmpInst::FCMP_OLE] = {
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{RTLIB::OLE_F32, CmpInst::BAD_ICMP_PREDICATE}};
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FCmp32Libcalls[CmpInst::FCMP_OLT] = {
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{RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}};
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FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}};
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FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_EQ}};
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FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_EQ}};
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FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_EQ}};
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FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_EQ}};
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FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_EQ}};
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FCmp32Libcalls[CmpInst::FCMP_UNO] = {
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{RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}};
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FCmp32Libcalls[CmpInst::FCMP_ONE] = {
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{RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE},
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{RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}};
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FCmp32Libcalls[CmpInst::FCMP_UEQ] = {
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{RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE},
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{RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}};
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FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
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FCmp64Libcalls[CmpInst::FCMP_OEQ] = {
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{RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE}};
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FCmp64Libcalls[CmpInst::FCMP_OGE] = {
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{RTLIB::OGE_F64, CmpInst::BAD_ICMP_PREDICATE}};
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FCmp64Libcalls[CmpInst::FCMP_OGT] = {
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{RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE}};
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FCmp64Libcalls[CmpInst::FCMP_OLE] = {
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{RTLIB::OLE_F64, CmpInst::BAD_ICMP_PREDICATE}};
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FCmp64Libcalls[CmpInst::FCMP_OLT] = {
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{RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}};
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FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}};
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FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_EQ}};
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FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_EQ}};
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FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_EQ}};
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FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_EQ}};
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FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_EQ}};
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FCmp64Libcalls[CmpInst::FCMP_UNO] = {
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{RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}};
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FCmp64Libcalls[CmpInst::FCMP_ONE] = {
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{RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE},
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{RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}};
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FCmp64Libcalls[CmpInst::FCMP_UEQ] = {
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{RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE},
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{RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}};
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}
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void ARMLegalizerInfo::setFCmpLibcallsGNU() {
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// FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be
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// default-initialized.
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FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
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FCmp32Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ}};
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FCmp32Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F32, CmpInst::ICMP_SGE}};
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FCmp32Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT}};
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FCmp32Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F32, CmpInst::ICMP_SLE}};
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FCmp32Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F32, CmpInst::ICMP_SLT}};
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FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}};
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FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_SGE}};
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FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_SGT}};
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FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SLE}};
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FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_SLT}};
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FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_NE}};
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FCmp32Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F32, CmpInst::ICMP_NE}};
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FCmp32Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT},
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{RTLIB::OLT_F32, CmpInst::ICMP_SLT}};
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FCmp32Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ},
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{RTLIB::UO_F32, CmpInst::ICMP_NE}};
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FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
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FCmp64Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ}};
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FCmp64Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F64, CmpInst::ICMP_SGE}};
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FCmp64Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT}};
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FCmp64Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F64, CmpInst::ICMP_SLE}};
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FCmp64Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F64, CmpInst::ICMP_SLT}};
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FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}};
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FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_SGE}};
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FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_SGT}};
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FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SLE}};
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FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_SLT}};
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FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_NE}};
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FCmp64Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F64, CmpInst::ICMP_NE}};
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FCmp64Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT},
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{RTLIB::OLT_F64, CmpInst::ICMP_SLT}};
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FCmp64Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ},
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{RTLIB::UO_F64, CmpInst::ICMP_NE}};
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}
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ARMLegalizerInfo::FCmpLibcallsList
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ARMLegalizerInfo::getFCmpLibcalls(CmpInst::Predicate Predicate,
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unsigned Size) const {
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assert(CmpInst::isFPPredicate(Predicate) && "Unsupported FCmp predicate");
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if (Size == 32)
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return FCmp32Libcalls[Predicate];
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if (Size == 64)
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return FCmp64Libcalls[Predicate];
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llvm_unreachable("Unsupported size for FCmp predicate");
|
|
}
|
|
|
|
bool ARMLegalizerInfo::legalizeCustom(MachineInstr &MI,
|
|
MachineRegisterInfo &MRI,
|
|
MachineIRBuilder &MIRBuilder,
|
|
GISelChangeObserver &Observer) const {
|
|
using namespace TargetOpcode;
|
|
|
|
MIRBuilder.setInstr(MI);
|
|
LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
|
|
|
|
switch (MI.getOpcode()) {
|
|
default:
|
|
return false;
|
|
case G_SREM:
|
|
case G_UREM: {
|
|
Register OriginalResult = MI.getOperand(0).getReg();
|
|
auto Size = MRI.getType(OriginalResult).getSizeInBits();
|
|
if (Size != 32)
|
|
return false;
|
|
|
|
auto Libcall =
|
|
MI.getOpcode() == G_SREM ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
|
|
|
|
// Our divmod libcalls return a struct containing the quotient and the
|
|
// remainder. Create a new, unused register for the quotient and use the
|
|
// destination of the original instruction for the remainder.
|
|
Type *ArgTy = Type::getInt32Ty(Ctx);
|
|
StructType *RetTy = StructType::get(Ctx, {ArgTy, ArgTy}, /* Packed */ true);
|
|
Register RetRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
|
|
OriginalResult};
|
|
auto Status = createLibcall(MIRBuilder, Libcall, {RetRegs, RetTy},
|
|
{{MI.getOperand(1).getReg(), ArgTy},
|
|
{MI.getOperand(2).getReg(), ArgTy}});
|
|
if (Status != LegalizerHelper::Legalized)
|
|
return false;
|
|
break;
|
|
}
|
|
case G_FCMP: {
|
|
assert(MRI.getType(MI.getOperand(2).getReg()) ==
|
|
MRI.getType(MI.getOperand(3).getReg()) &&
|
|
"Mismatched operands for G_FCMP");
|
|
auto OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
|
|
|
|
auto OriginalResult = MI.getOperand(0).getReg();
|
|
auto Predicate =
|
|
static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
|
|
auto Libcalls = getFCmpLibcalls(Predicate, OpSize);
|
|
|
|
if (Libcalls.empty()) {
|
|
assert((Predicate == CmpInst::FCMP_TRUE ||
|
|
Predicate == CmpInst::FCMP_FALSE) &&
|
|
"Predicate needs libcalls, but none specified");
|
|
MIRBuilder.buildConstant(OriginalResult,
|
|
Predicate == CmpInst::FCMP_TRUE ? 1 : 0);
|
|
MI.eraseFromParent();
|
|
return true;
|
|
}
|
|
|
|
assert((OpSize == 32 || OpSize == 64) && "Unsupported operand size");
|
|
auto *ArgTy = OpSize == 32 ? Type::getFloatTy(Ctx) : Type::getDoubleTy(Ctx);
|
|
auto *RetTy = Type::getInt32Ty(Ctx);
|
|
|
|
SmallVector<Register, 2> Results;
|
|
for (auto Libcall : Libcalls) {
|
|
auto LibcallResult = MRI.createGenericVirtualRegister(LLT::scalar(32));
|
|
auto Status =
|
|
createLibcall(MIRBuilder, Libcall.LibcallID, {LibcallResult, RetTy},
|
|
{{MI.getOperand(2).getReg(), ArgTy},
|
|
{MI.getOperand(3).getReg(), ArgTy}});
|
|
|
|
if (Status != LegalizerHelper::Legalized)
|
|
return false;
|
|
|
|
auto ProcessedResult =
|
|
Libcalls.size() == 1
|
|
? OriginalResult
|
|
: MRI.createGenericVirtualRegister(MRI.getType(OriginalResult));
|
|
|
|
// We have a result, but we need to transform it into a proper 1-bit 0 or
|
|
// 1, taking into account the different peculiarities of the values
|
|
// returned by the comparison functions.
|
|
CmpInst::Predicate ResultPred = Libcall.Predicate;
|
|
if (ResultPred == CmpInst::BAD_ICMP_PREDICATE) {
|
|
// We have a nice 0 or 1, and we just need to truncate it back to 1 bit
|
|
// to keep the types consistent.
|
|
MIRBuilder.buildTrunc(ProcessedResult, LibcallResult);
|
|
} else {
|
|
// We need to compare against 0.
|
|
assert(CmpInst::isIntPredicate(ResultPred) && "Unsupported predicate");
|
|
auto Zero = MRI.createGenericVirtualRegister(LLT::scalar(32));
|
|
MIRBuilder.buildConstant(Zero, 0);
|
|
MIRBuilder.buildICmp(ResultPred, ProcessedResult, LibcallResult, Zero);
|
|
}
|
|
Results.push_back(ProcessedResult);
|
|
}
|
|
|
|
if (Results.size() != 1) {
|
|
assert(Results.size() == 2 && "Unexpected number of results");
|
|
MIRBuilder.buildOr(OriginalResult, Results[0], Results[1]);
|
|
}
|
|
break;
|
|
}
|
|
case G_FCONSTANT: {
|
|
// Convert to integer constants, while preserving the binary representation.
|
|
auto AsInteger =
|
|
MI.getOperand(1).getFPImm()->getValueAPF().bitcastToAPInt();
|
|
MIRBuilder.buildConstant(MI.getOperand(0).getReg(),
|
|
*ConstantInt::get(Ctx, AsInteger));
|
|
break;
|
|
}
|
|
}
|
|
|
|
MI.eraseFromParent();
|
|
return true;
|
|
}
|