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5cb67c7c9d
Teach RegisterBankInfo to use the correct register class, and tell the legalizer it's legal. Everything else just works. The one thing that's slightly weird about this compared to SelectionDAG isel is that legalization can't distinguish between i64 and <1 x i64>, so we might end up with more NEON instructions than the user expects. Differential Revision: https://reviews.llvm.org/D63585 llvm-svn: 363989
484 lines
18 KiB
C++
484 lines
18 KiB
C++
//===- ARMRegisterBankInfo.cpp -----------------------------------*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the targeting of the RegisterBankInfo class for ARM.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#include "ARMRegisterBankInfo.h"
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#include "ARMInstrInfo.h" // For the register classes
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#include "ARMSubtarget.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#define GET_TARGET_REGBANK_IMPL
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#include "ARMGenRegisterBank.inc"
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using namespace llvm;
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// FIXME: TableGen this.
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// If it grows too much and TableGen still isn't ready to do the job, extract it
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// into an ARMGenRegisterBankInfo.def (similar to AArch64).
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namespace llvm {
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namespace ARM {
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enum PartialMappingIdx {
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PMI_GPR,
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PMI_SPR,
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PMI_DPR,
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PMI_Min = PMI_GPR,
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};
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RegisterBankInfo::PartialMapping PartMappings[]{
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// GPR Partial Mapping
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{0, 32, GPRRegBank},
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// SPR Partial Mapping
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{0, 32, FPRRegBank},
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// DPR Partial Mapping
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{0, 64, FPRRegBank},
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};
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#ifndef NDEBUG
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static bool checkPartMapping(const RegisterBankInfo::PartialMapping &PM,
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unsigned Start, unsigned Length,
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unsigned RegBankID) {
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return PM.StartIdx == Start && PM.Length == Length &&
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PM.RegBank->getID() == RegBankID;
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}
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static void checkPartialMappings() {
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assert(
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checkPartMapping(PartMappings[PMI_GPR - PMI_Min], 0, 32, GPRRegBankID) &&
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"Wrong mapping for GPR");
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assert(
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checkPartMapping(PartMappings[PMI_SPR - PMI_Min], 0, 32, FPRRegBankID) &&
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"Wrong mapping for SPR");
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assert(
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checkPartMapping(PartMappings[PMI_DPR - PMI_Min], 0, 64, FPRRegBankID) &&
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"Wrong mapping for DPR");
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}
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#endif
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enum ValueMappingIdx {
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InvalidIdx = 0,
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GPR3OpsIdx = 1,
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SPR3OpsIdx = 4,
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DPR3OpsIdx = 7,
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};
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RegisterBankInfo::ValueMapping ValueMappings[] = {
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// invalid
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{nullptr, 0},
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// 3 ops in GPRs
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{&PartMappings[PMI_GPR - PMI_Min], 1},
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{&PartMappings[PMI_GPR - PMI_Min], 1},
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{&PartMappings[PMI_GPR - PMI_Min], 1},
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// 3 ops in SPRs
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{&PartMappings[PMI_SPR - PMI_Min], 1},
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{&PartMappings[PMI_SPR - PMI_Min], 1},
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{&PartMappings[PMI_SPR - PMI_Min], 1},
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// 3 ops in DPRs
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{&PartMappings[PMI_DPR - PMI_Min], 1},
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{&PartMappings[PMI_DPR - PMI_Min], 1},
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{&PartMappings[PMI_DPR - PMI_Min], 1}};
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#ifndef NDEBUG
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static bool checkValueMapping(const RegisterBankInfo::ValueMapping &VM,
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RegisterBankInfo::PartialMapping *BreakDown) {
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return VM.NumBreakDowns == 1 && VM.BreakDown == BreakDown;
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}
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static void checkValueMappings() {
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assert(checkValueMapping(ValueMappings[GPR3OpsIdx],
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&PartMappings[PMI_GPR - PMI_Min]) &&
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"Wrong value mapping for 3 GPR ops instruction");
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assert(checkValueMapping(ValueMappings[GPR3OpsIdx + 1],
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&PartMappings[PMI_GPR - PMI_Min]) &&
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"Wrong value mapping for 3 GPR ops instruction");
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assert(checkValueMapping(ValueMappings[GPR3OpsIdx + 2],
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&PartMappings[PMI_GPR - PMI_Min]) &&
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"Wrong value mapping for 3 GPR ops instruction");
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assert(checkValueMapping(ValueMappings[SPR3OpsIdx],
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&PartMappings[PMI_SPR - PMI_Min]) &&
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"Wrong value mapping for 3 SPR ops instruction");
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assert(checkValueMapping(ValueMappings[SPR3OpsIdx + 1],
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&PartMappings[PMI_SPR - PMI_Min]) &&
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"Wrong value mapping for 3 SPR ops instruction");
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assert(checkValueMapping(ValueMappings[SPR3OpsIdx + 2],
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&PartMappings[PMI_SPR - PMI_Min]) &&
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"Wrong value mapping for 3 SPR ops instruction");
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assert(checkValueMapping(ValueMappings[DPR3OpsIdx],
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&PartMappings[PMI_DPR - PMI_Min]) &&
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"Wrong value mapping for 3 DPR ops instruction");
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assert(checkValueMapping(ValueMappings[DPR3OpsIdx + 1],
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&PartMappings[PMI_DPR - PMI_Min]) &&
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"Wrong value mapping for 3 DPR ops instruction");
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assert(checkValueMapping(ValueMappings[DPR3OpsIdx + 2],
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&PartMappings[PMI_DPR - PMI_Min]) &&
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"Wrong value mapping for 3 DPR ops instruction");
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}
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#endif
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} // end namespace arm
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} // end namespace llvm
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ARMRegisterBankInfo::ARMRegisterBankInfo(const TargetRegisterInfo &TRI)
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: ARMGenRegisterBankInfo() {
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static bool AlreadyInit = false;
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// We have only one set of register banks, whatever the subtarget
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// is. Therefore, the initialization of the RegBanks table should be
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// done only once. Indeed the table of all register banks
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// (ARM::RegBanks) is unique in the compiler. At some point, it
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// will get tablegen'ed and the whole constructor becomes empty.
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if (AlreadyInit)
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return;
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AlreadyInit = true;
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const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID);
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(void)RBGPR;
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assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up");
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// Initialize the GPR bank.
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assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) &&
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"Subclass not added?");
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assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) &&
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"Subclass not added?");
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assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) &&
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"Subclass not added?");
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assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) &&
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"Subclass not added?");
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assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) &&
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"Subclass not added?");
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assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) &&
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"Subclass not added?");
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assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPR_and_tcGPRRegClassID)) &&
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"Subclass not added?");
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assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPREven_and_tGPR_and_tcGPRRegClassID)) &&
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"Subclass not added?");
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assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPROdd_and_tcGPRRegClassID)) &&
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"Subclass not added?");
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assert(RBGPR.getSize() == 32 && "GPRs should hold up to 32-bit");
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#ifndef NDEBUG
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ARM::checkPartialMappings();
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ARM::checkValueMappings();
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#endif
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}
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const RegisterBank &ARMRegisterBankInfo::getRegBankFromRegClass(
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const TargetRegisterClass &RC) const {
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using namespace ARM;
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switch (RC.getID()) {
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case GPRRegClassID:
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case GPRwithAPSRRegClassID:
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case GPRnopcRegClassID:
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case rGPRRegClassID:
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case GPRspRegClassID:
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case tGPR_and_tcGPRRegClassID:
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case tcGPRRegClassID:
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case tGPRRegClassID:
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case tGPREvenRegClassID:
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case tGPROddRegClassID:
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case tGPR_and_tGPREvenRegClassID:
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case tGPR_and_tGPROddRegClassID:
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case tGPREven_and_tcGPRRegClassID:
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case tGPREven_and_tGPR_and_tcGPRRegClassID:
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case tGPROdd_and_tcGPRRegClassID:
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return getRegBank(ARM::GPRRegBankID);
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case HPRRegClassID:
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case SPR_8RegClassID:
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case SPRRegClassID:
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case DPR_8RegClassID:
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case DPRRegClassID:
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case QPRRegClassID:
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return getRegBank(ARM::FPRRegBankID);
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default:
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llvm_unreachable("Unsupported register kind");
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}
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llvm_unreachable("Switch should handle all register classes");
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}
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const RegisterBankInfo::InstructionMapping &
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ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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auto Opc = MI.getOpcode();
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// Try the default logic for non-generic instructions that are either copies
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// or already have some operands assigned to banks.
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if (!isPreISelGenericOpcode(Opc) || Opc == TargetOpcode::G_PHI) {
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const InstructionMapping &Mapping = getInstrMappingImpl(MI);
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if (Mapping.isValid())
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return Mapping;
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}
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using namespace TargetOpcode;
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const MachineFunction &MF = *MI.getParent()->getParent();
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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unsigned NumOperands = MI.getNumOperands();
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const ValueMapping *OperandsMapping = &ARM::ValueMappings[ARM::GPR3OpsIdx];
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switch (Opc) {
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case G_ADD:
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case G_SUB: {
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// Integer operations where the source and destination are in the
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// same register class.
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LLT Ty = MRI.getType(MI.getOperand(0).getReg());
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OperandsMapping = Ty.getSizeInBits() == 64
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? &ARM::ValueMappings[ARM::DPR3OpsIdx]
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: &ARM::ValueMappings[ARM::GPR3OpsIdx];
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break;
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}
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case G_MUL:
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case G_AND:
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case G_OR:
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case G_XOR:
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case G_LSHR:
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case G_ASHR:
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case G_SHL:
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case G_SDIV:
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case G_UDIV:
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case G_SEXT:
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case G_ZEXT:
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case G_ANYEXT:
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case G_GEP:
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case G_INTTOPTR:
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case G_PTRTOINT:
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case G_CTLZ:
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// FIXME: We're abusing the fact that everything lives in a GPR for now; in
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// the real world we would use different mappings.
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OperandsMapping = &ARM::ValueMappings[ARM::GPR3OpsIdx];
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break;
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case G_TRUNC: {
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// In some cases we may end up with a G_TRUNC from a 64-bit value to a
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// 32-bit value. This isn't a real floating point trunc (that would be a
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// G_FPTRUNC). Instead it is an integer trunc in disguise, which can appear
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// because the legalizer doesn't distinguish between integer and floating
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// point values so it may leave some 64-bit integers un-narrowed. Until we
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// have a more principled solution that doesn't let such things sneak all
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// the way to this point, just map the source to a DPR and the destination
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// to a GPR.
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LLT LargeTy = MRI.getType(MI.getOperand(1).getReg());
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OperandsMapping =
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LargeTy.getSizeInBits() <= 32
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? &ARM::ValueMappings[ARM::GPR3OpsIdx]
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: getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx],
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&ARM::ValueMappings[ARM::DPR3OpsIdx]});
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break;
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}
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case G_LOAD:
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case G_STORE: {
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LLT Ty = MRI.getType(MI.getOperand(0).getReg());
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OperandsMapping =
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Ty.getSizeInBits() == 64
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? getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx],
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&ARM::ValueMappings[ARM::GPR3OpsIdx]})
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: &ARM::ValueMappings[ARM::GPR3OpsIdx];
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break;
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}
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case G_FADD:
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case G_FSUB:
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case G_FMUL:
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case G_FDIV:
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case G_FNEG: {
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LLT Ty = MRI.getType(MI.getOperand(0).getReg());
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OperandsMapping =Ty.getSizeInBits() == 64
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? &ARM::ValueMappings[ARM::DPR3OpsIdx]
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: &ARM::ValueMappings[ARM::SPR3OpsIdx];
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break;
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}
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case G_FMA: {
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LLT Ty = MRI.getType(MI.getOperand(0).getReg());
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OperandsMapping =
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Ty.getSizeInBits() == 64
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? getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx],
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&ARM::ValueMappings[ARM::DPR3OpsIdx],
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&ARM::ValueMappings[ARM::DPR3OpsIdx],
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&ARM::ValueMappings[ARM::DPR3OpsIdx]})
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: getOperandsMapping({&ARM::ValueMappings[ARM::SPR3OpsIdx],
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&ARM::ValueMappings[ARM::SPR3OpsIdx],
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&ARM::ValueMappings[ARM::SPR3OpsIdx],
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&ARM::ValueMappings[ARM::SPR3OpsIdx]});
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break;
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}
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case G_FPEXT: {
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LLT ToTy = MRI.getType(MI.getOperand(0).getReg());
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LLT FromTy = MRI.getType(MI.getOperand(1).getReg());
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if (ToTy.getSizeInBits() == 64 && FromTy.getSizeInBits() == 32)
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OperandsMapping =
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getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx],
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&ARM::ValueMappings[ARM::SPR3OpsIdx]});
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break;
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}
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case G_FPTRUNC: {
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LLT ToTy = MRI.getType(MI.getOperand(0).getReg());
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LLT FromTy = MRI.getType(MI.getOperand(1).getReg());
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if (ToTy.getSizeInBits() == 32 && FromTy.getSizeInBits() == 64)
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OperandsMapping =
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getOperandsMapping({&ARM::ValueMappings[ARM::SPR3OpsIdx],
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&ARM::ValueMappings[ARM::DPR3OpsIdx]});
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break;
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}
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case G_FPTOSI:
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case G_FPTOUI: {
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LLT ToTy = MRI.getType(MI.getOperand(0).getReg());
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LLT FromTy = MRI.getType(MI.getOperand(1).getReg());
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if ((FromTy.getSizeInBits() == 32 || FromTy.getSizeInBits() == 64) &&
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ToTy.getSizeInBits() == 32)
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OperandsMapping =
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FromTy.getSizeInBits() == 64
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? getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx],
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&ARM::ValueMappings[ARM::DPR3OpsIdx]})
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: getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx],
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&ARM::ValueMappings[ARM::SPR3OpsIdx]});
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break;
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}
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case G_SITOFP:
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case G_UITOFP: {
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LLT ToTy = MRI.getType(MI.getOperand(0).getReg());
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LLT FromTy = MRI.getType(MI.getOperand(1).getReg());
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if (FromTy.getSizeInBits() == 32 &&
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(ToTy.getSizeInBits() == 32 || ToTy.getSizeInBits() == 64))
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OperandsMapping =
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ToTy.getSizeInBits() == 64
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? getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx],
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&ARM::ValueMappings[ARM::GPR3OpsIdx]})
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: getOperandsMapping({&ARM::ValueMappings[ARM::SPR3OpsIdx],
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&ARM::ValueMappings[ARM::GPR3OpsIdx]});
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break;
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}
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case G_FCONSTANT: {
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LLT Ty = MRI.getType(MI.getOperand(0).getReg());
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OperandsMapping = getOperandsMapping(
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{Ty.getSizeInBits() == 64 ? &ARM::ValueMappings[ARM::DPR3OpsIdx]
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: &ARM::ValueMappings[ARM::SPR3OpsIdx],
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nullptr});
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break;
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}
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case G_CONSTANT:
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case G_FRAME_INDEX:
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case G_GLOBAL_VALUE:
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OperandsMapping =
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getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr});
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break;
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case G_SELECT: {
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LLT Ty = MRI.getType(MI.getOperand(0).getReg());
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(void)Ty;
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LLT Ty2 = MRI.getType(MI.getOperand(1).getReg());
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(void)Ty2;
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assert(Ty.getSizeInBits() == 32 && "Unsupported size for G_SELECT");
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assert(Ty2.getSizeInBits() == 1 && "Unsupported size for G_SELECT");
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OperandsMapping =
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getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx],
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&ARM::ValueMappings[ARM::GPR3OpsIdx],
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&ARM::ValueMappings[ARM::GPR3OpsIdx],
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&ARM::ValueMappings[ARM::GPR3OpsIdx]});
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break;
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}
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case G_ICMP: {
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LLT Ty2 = MRI.getType(MI.getOperand(2).getReg());
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(void)Ty2;
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assert(Ty2.getSizeInBits() == 32 && "Unsupported size for G_ICMP");
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OperandsMapping =
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getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr,
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&ARM::ValueMappings[ARM::GPR3OpsIdx],
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&ARM::ValueMappings[ARM::GPR3OpsIdx]});
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break;
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}
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case G_FCMP: {
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LLT Ty = MRI.getType(MI.getOperand(0).getReg());
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(void)Ty;
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LLT Ty1 = MRI.getType(MI.getOperand(2).getReg());
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LLT Ty2 = MRI.getType(MI.getOperand(3).getReg());
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(void)Ty2;
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assert(Ty.getSizeInBits() == 1 && "Unsupported size for G_FCMP");
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assert(Ty1.getSizeInBits() == Ty2.getSizeInBits() &&
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"Mismatched operand sizes for G_FCMP");
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unsigned Size = Ty1.getSizeInBits();
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assert((Size == 32 || Size == 64) && "Unsupported size for G_FCMP");
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auto FPRValueMapping = Size == 32 ? &ARM::ValueMappings[ARM::SPR3OpsIdx]
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: &ARM::ValueMappings[ARM::DPR3OpsIdx];
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OperandsMapping =
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getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr,
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FPRValueMapping, FPRValueMapping});
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break;
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}
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case G_MERGE_VALUES: {
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// We only support G_MERGE_VALUES for creating a double precision floating
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// point value out of two GPRs.
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LLT Ty = MRI.getType(MI.getOperand(0).getReg());
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LLT Ty1 = MRI.getType(MI.getOperand(1).getReg());
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LLT Ty2 = MRI.getType(MI.getOperand(2).getReg());
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if (Ty.getSizeInBits() != 64 || Ty1.getSizeInBits() != 32 ||
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Ty2.getSizeInBits() != 32)
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return getInvalidInstructionMapping();
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OperandsMapping =
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getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx],
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&ARM::ValueMappings[ARM::GPR3OpsIdx],
|
|
&ARM::ValueMappings[ARM::GPR3OpsIdx]});
|
|
break;
|
|
}
|
|
case G_UNMERGE_VALUES: {
|
|
// We only support G_UNMERGE_VALUES for splitting a double precision
|
|
// floating point value into two GPRs.
|
|
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
|
|
LLT Ty1 = MRI.getType(MI.getOperand(1).getReg());
|
|
LLT Ty2 = MRI.getType(MI.getOperand(2).getReg());
|
|
if (Ty.getSizeInBits() != 32 || Ty1.getSizeInBits() != 32 ||
|
|
Ty2.getSizeInBits() != 64)
|
|
return getInvalidInstructionMapping();
|
|
OperandsMapping =
|
|
getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx],
|
|
&ARM::ValueMappings[ARM::GPR3OpsIdx],
|
|
&ARM::ValueMappings[ARM::DPR3OpsIdx]});
|
|
break;
|
|
}
|
|
case G_BR:
|
|
OperandsMapping = getOperandsMapping({nullptr});
|
|
break;
|
|
case G_BRCOND:
|
|
OperandsMapping =
|
|
getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr});
|
|
break;
|
|
case DBG_VALUE: {
|
|
SmallVector<const ValueMapping *, 4> OperandBanks(NumOperands);
|
|
const MachineOperand &MaybeReg = MI.getOperand(0);
|
|
if (MaybeReg.isReg() && MaybeReg.getReg()) {
|
|
unsigned Size = MRI.getType(MaybeReg.getReg()).getSizeInBits();
|
|
if (Size > 32 && Size != 64)
|
|
return getInvalidInstructionMapping();
|
|
OperandBanks[0] = Size == 64 ? &ARM::ValueMappings[ARM::DPR3OpsIdx]
|
|
: &ARM::ValueMappings[ARM::GPR3OpsIdx];
|
|
}
|
|
OperandsMapping = getOperandsMapping(OperandBanks);
|
|
break;
|
|
}
|
|
default:
|
|
return getInvalidInstructionMapping();
|
|
}
|
|
|
|
#ifndef NDEBUG
|
|
for (unsigned i = 0; i < NumOperands; i++) {
|
|
for (const auto &Mapping : OperandsMapping[i]) {
|
|
assert(
|
|
(Mapping.RegBank->getID() != ARM::FPRRegBankID ||
|
|
MF.getSubtarget<ARMSubtarget>().hasVFP2Base()) &&
|
|
"Trying to use floating point register bank on target without vfp");
|
|
}
|
|
}
|
|
#endif
|
|
|
|
return getInstructionMapping(DefaultMappingID, /*Cost=*/1, OperandsMapping,
|
|
NumOperands);
|
|
}
|