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a3957bd3b3
This patch adds a simple Cortex-M4 schedule, renaming the existing M3 schedule to M4 and filling in the latencies as-per the Cortex-M4 TRM: https://developer.arm.com/docs/ddi0439/latest Most of these are 1, with the important exception being loads taking 2 cycles. A few others are also higher, but I don't believe they make a large difference. I've repurposed the M3 schedule as the latencies are mostly the same between the two cores, with the M4 having more FP and DSP instructions. We also turn on MISched and UseAA for the cores that now use this. It also adds some schedule Write's to various instruction to make things simpler. Differential Revision: https://reviews.llvm.org/D54142 llvm-svn: 360768
120 lines
3.7 KiB
TableGen
120 lines
3.7 KiB
TableGen
//==- ARMScheduleM4.td - Cortex-M4 Scheduling Definitions -*- tablegen -*-====//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the SchedRead/Write data for the ARM Cortex-M4 processor.
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//
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//===----------------------------------------------------------------------===//
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def CortexM4Model : SchedMachineModel {
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let IssueWidth = 1; // Only IT can be dual-issued, so assume single-issue
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let MicroOpBufferSize = 0; // In-order
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let LoadLatency = 2; // Latency when not pipelined, not pc-relative
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let MispredictPenalty = 2; // Best case branch taken cost
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let PostRAScheduler = 1;
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let CompleteModel = 0;
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}
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// We model the entire cpu as a single pipeline with a BufferSize = 0 since
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// Cortex-M4 is in-order.
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def M4Unit : ProcResource<1> { let BufferSize = 0; }
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let SchedModel = CortexM4Model in {
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// Some definitions of latencies we apply to different instructions
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class M4UnitL1<SchedWrite write> : WriteRes<write, [M4Unit]> { let Latency = 1; }
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class M4UnitL2<SchedWrite write> : WriteRes<write, [M4Unit]> { let Latency = 2; }
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class M4UnitL3<SchedWrite write> : WriteRes<write, [M4Unit]> { let Latency = 3; }
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class M4UnitL14<SchedWrite write> : WriteRes<write, [M4Unit]> { let Latency = 14; }
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def M4UnitL1_wr : SchedWriteRes<[M4Unit]> { let Latency = 1; }
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def M4UnitL2_wr : SchedWriteRes<[M4Unit]> { let Latency = 2; }
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class M4UnitL1I<dag instr> : InstRW<[M4UnitL1_wr], instr>;
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class M4UnitL2I<dag instr> : InstRW<[M4UnitL2_wr], instr>;
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// Loads, MAC's and DIV all get a higher latency of 2
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def : M4UnitL2<WriteLd>;
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def : M4UnitL2<WriteMAC32>;
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def : M4UnitL2<WriteMAC64Hi>;
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def : M4UnitL2<WriteMAC64Lo>;
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def : M4UnitL2<WriteMAC16>;
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def : M4UnitL2<WriteDIV>;
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def : M4UnitL2I<(instregex "(t|t2)LDM")>;
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// Stores we use a latency of 1 as they have no outputs
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def : M4UnitL1<WriteST>;
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def : M4UnitL1I<(instregex "(t|t2)STM")>;
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// Everything else has a Latency of 1
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def : M4UnitL1<WriteALU>;
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def : M4UnitL1<WriteALUsi>;
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def : M4UnitL1<WriteALUsr>;
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def : M4UnitL1<WriteALUSsr>;
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def : M4UnitL1<WriteBr>;
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def : M4UnitL1<WriteBrL>;
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def : M4UnitL1<WriteBrTbl>;
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def : M4UnitL1<WriteCMPsi>;
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def : M4UnitL1<WriteCMPsr>;
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def : M4UnitL1<WriteCMP>;
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def : M4UnitL1<WriteMUL32>;
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def : M4UnitL1<WriteMUL64Hi>;
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def : M4UnitL1<WriteMUL64Lo>;
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def : M4UnitL1<WriteMUL16>;
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def : M4UnitL1<WriteNoop>;
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def : M4UnitL1<WritePreLd>;
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def : M4UnitL1I<(instregex "(t|t2)MOV")>;
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def : M4UnitL1I<(instrs COPY)>;
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def : M4UnitL1I<(instregex "t2IT")>;
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def : M4UnitL1I<(instregex "t2SEL", "t2USAD8",
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"t2(S|Q|SH|U|UQ|UH)(ADD16|ASX|SAX|SUB16|ADD8|SUB8)", "t2USADA8", "(t|t2)REV")>;
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def : ReadAdvance<ReadALU, 0>;
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def : ReadAdvance<ReadALUsr, 0>;
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def : ReadAdvance<ReadMUL, 0>;
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def : ReadAdvance<ReadMAC, 0>;
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// Most FP instructions are single-cycle latency, except MAC's, Div's and Sqrt's.
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// Loads still take 2 cycles.
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def : M4UnitL1<WriteFPCVT>;
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def : M4UnitL1<WriteFPMOV>;
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def : M4UnitL1<WriteFPALU32>;
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def : M4UnitL1<WriteFPALU64>;
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def : M4UnitL1<WriteFPMUL32>;
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def : M4UnitL1<WriteFPMUL64>;
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def : M4UnitL2I<(instregex "VLD")>;
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def : M4UnitL1I<(instregex "VST")>;
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def : M4UnitL3<WriteFPMAC32>;
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def : M4UnitL3<WriteFPMAC64>;
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def : M4UnitL14<WriteFPDIV32>;
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def : M4UnitL14<WriteFPDIV64>;
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def : M4UnitL14<WriteFPSQRT32>;
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def : M4UnitL14<WriteFPSQRT64>;
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def : M4UnitL1<WriteVLD1>;
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def : M4UnitL1<WriteVLD2>;
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def : M4UnitL1<WriteVLD3>;
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def : M4UnitL1<WriteVLD4>;
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def : M4UnitL1<WriteVST1>;
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def : M4UnitL1<WriteVST2>;
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def : M4UnitL1<WriteVST3>;
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def : M4UnitL1<WriteVST4>;
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def : ReadAdvance<ReadFPMUL, 0>;
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def : ReadAdvance<ReadFPMAC, 0>;
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}
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