mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-19 11:02:59 +02:00
6dccf8a815
A refactor in r364191 changed register types from an unsigned int to the llvm:Register class. Adjust the AVR backend to this change. This fixes build errors when building with the experimental AVR backend enabled. Differential Revision: https://reviews.llvm.org/D63776 llvm-svn: 364330
70 lines
2.4 KiB
C++
70 lines
2.4 KiB
C++
//===-- AVRRegisterInfo.h - AVR Register Information Impl -------*- C++ -*-===//
|
|
//
|
|
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
|
// See https://llvm.org/LICENSE.txt for license information.
|
|
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file contains the AVR implementation of the TargetRegisterInfo class.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef LLVM_AVR_REGISTER_INFO_H
|
|
#define LLVM_AVR_REGISTER_INFO_H
|
|
|
|
#include "llvm/CodeGen/TargetRegisterInfo.h"
|
|
|
|
#define GET_REGINFO_HEADER
|
|
#include "AVRGenRegisterInfo.inc"
|
|
|
|
namespace llvm {
|
|
|
|
/// Utilities relating to AVR registers.
|
|
class AVRRegisterInfo : public AVRGenRegisterInfo {
|
|
public:
|
|
AVRRegisterInfo();
|
|
|
|
public:
|
|
const uint16_t *
|
|
getCalleeSavedRegs(const MachineFunction *MF = 0) const override;
|
|
const uint32_t *getCallPreservedMask(const MachineFunction &MF,
|
|
CallingConv::ID CC) const override;
|
|
BitVector getReservedRegs(const MachineFunction &MF) const override;
|
|
|
|
const TargetRegisterClass *
|
|
getLargestLegalSuperClass(const TargetRegisterClass *RC,
|
|
const MachineFunction &MF) const override;
|
|
|
|
/// Stack Frame Processing Methods
|
|
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
|
|
unsigned FIOperandNum,
|
|
RegScavenger *RS = NULL) const override;
|
|
|
|
Register getFrameRegister(const MachineFunction &MF) const override;
|
|
|
|
const TargetRegisterClass *
|
|
getPointerRegClass(const MachineFunction &MF,
|
|
unsigned Kind = 0) const override;
|
|
|
|
/// Splits a 16-bit `DREGS` register into the lo/hi register pair.
|
|
/// \param Reg A 16-bit register to split.
|
|
void splitReg(unsigned Reg, unsigned &LoReg, unsigned &HiReg) const;
|
|
|
|
bool trackLivenessAfterRegAlloc(const MachineFunction &) const override {
|
|
return true;
|
|
}
|
|
|
|
bool shouldCoalesce(MachineInstr *MI,
|
|
const TargetRegisterClass *SrcRC,
|
|
unsigned SubReg,
|
|
const TargetRegisterClass *DstRC,
|
|
unsigned DstSubReg,
|
|
const TargetRegisterClass *NewRC,
|
|
LiveIntervals &LIS) const override;
|
|
};
|
|
|
|
} // end namespace llvm
|
|
|
|
#endif // LLVM_AVR_REGISTER_INFO_H
|