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to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
65 lines
2.5 KiB
C++
65 lines
2.5 KiB
C++
//===---------------------------- Context.cpp -------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// This file defines a class for holding ownership of various simulated
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/// hardware units. A Context also provides a utility routine for constructing
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/// a default out-of-order pipeline with fetch, dispatch, execute, and retire
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/// stages.
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///
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//===----------------------------------------------------------------------===//
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#include "llvm/MCA/Context.h"
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#include "llvm/MCA/HardwareUnits/RegisterFile.h"
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#include "llvm/MCA/HardwareUnits/RetireControlUnit.h"
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#include "llvm/MCA/HardwareUnits/Scheduler.h"
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#include "llvm/MCA/Stages/DispatchStage.h"
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#include "llvm/MCA/Stages/EntryStage.h"
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#include "llvm/MCA/Stages/ExecuteStage.h"
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#include "llvm/MCA/Stages/RetireStage.h"
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namespace llvm {
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namespace mca {
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std::unique_ptr<Pipeline>
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Context::createDefaultPipeline(const PipelineOptions &Opts, InstrBuilder &IB,
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SourceMgr &SrcMgr) {
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const MCSchedModel &SM = STI.getSchedModel();
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// Create the hardware units defining the backend.
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auto RCU = llvm::make_unique<RetireControlUnit>(SM);
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auto PRF = llvm::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize);
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auto LSU = llvm::make_unique<LSUnit>(SM, Opts.LoadQueueSize,
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Opts.StoreQueueSize, Opts.AssumeNoAlias);
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auto HWS = llvm::make_unique<Scheduler>(SM, *LSU);
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// Create the pipeline stages.
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auto Fetch = llvm::make_unique<EntryStage>(SrcMgr);
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auto Dispatch = llvm::make_unique<DispatchStage>(STI, MRI, Opts.DispatchWidth,
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*RCU, *PRF);
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auto Execute = llvm::make_unique<ExecuteStage>(*HWS);
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auto Retire = llvm::make_unique<RetireStage>(*RCU, *PRF);
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// Pass the ownership of all the hardware units to this Context.
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addHardwareUnit(std::move(RCU));
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addHardwareUnit(std::move(PRF));
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addHardwareUnit(std::move(LSU));
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addHardwareUnit(std::move(HWS));
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// Build the pipeline.
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auto StagePipeline = llvm::make_unique<Pipeline>();
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StagePipeline->appendStage(std::move(Fetch));
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StagePipeline->appendStage(std::move(Dispatch));
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StagePipeline->appendStage(std::move(Execute));
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StagePipeline->appendStage(std::move(Retire));
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return StagePipeline;
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}
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} // namespace mca
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} // namespace llvm
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