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136e458b75
For now CUDA-9 is not included in the list of CUDA versions clang searches for, so the path to CUDA-9 must be explicitly passed via --cuda-path=. On LLVM side NVPTX added sm_70 GPU type which bumps required PTX version to 6.0, but otherwise is equivalent to sm_62 at the moment. Differential Revision: https://reviews.llvm.org/D37576 llvm-svn: 312734
102 lines
4.2 KiB
TableGen
102 lines
4.2 KiB
TableGen
//===- NVPTX.td - Describe the NVPTX Target Machine -----------*- tblgen -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// This is the top level entry point for the NVPTX target.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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include "NVPTXRegisterInfo.td"
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include "NVPTXInstrInfo.td"
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//===----------------------------------------------------------------------===//
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// Subtarget Features.
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// - We use the SM version number instead of explicit feature table.
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// - Need at least one feature to avoid generating zero sized array by
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// TableGen in NVPTXGenSubtarget.inc.
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//===----------------------------------------------------------------------===//
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// SM Versions
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def SM20 : SubtargetFeature<"sm_20", "SmVersion", "20",
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"Target SM 2.0">;
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def SM21 : SubtargetFeature<"sm_21", "SmVersion", "21",
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"Target SM 2.1">;
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def SM30 : SubtargetFeature<"sm_30", "SmVersion", "30",
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"Target SM 3.0">;
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def SM32 : SubtargetFeature<"sm_32", "SmVersion", "32",
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"Target SM 3.2">;
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def SM35 : SubtargetFeature<"sm_35", "SmVersion", "35",
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"Target SM 3.5">;
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def SM37 : SubtargetFeature<"sm_37", "SmVersion", "37",
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"Target SM 3.7">;
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def SM50 : SubtargetFeature<"sm_50", "SmVersion", "50",
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"Target SM 5.0">;
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def SM52 : SubtargetFeature<"sm_52", "SmVersion", "52",
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"Target SM 5.2">;
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def SM53 : SubtargetFeature<"sm_53", "SmVersion", "53",
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"Target SM 5.3">;
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def SM60 : SubtargetFeature<"sm_60", "SmVersion", "60",
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"Target SM 6.0">;
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def SM61 : SubtargetFeature<"sm_61", "SmVersion", "61",
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"Target SM 6.1">;
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def SM62 : SubtargetFeature<"sm_62", "SmVersion", "62",
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"Target SM 6.2">;
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def SM70 : SubtargetFeature<"sm_70", "SmVersion", "70",
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"Target SM 7.0">;
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def SATOM : SubtargetFeature<"satom", "HasAtomScope", "true",
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"Atomic operations with scope">;
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// PTX Versions
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def PTX32 : SubtargetFeature<"ptx32", "PTXVersion", "32",
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"Use PTX version 3.2">;
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def PTX40 : SubtargetFeature<"ptx40", "PTXVersion", "40",
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"Use PTX version 4.0">;
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def PTX41 : SubtargetFeature<"ptx41", "PTXVersion", "41",
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"Use PTX version 4.1">;
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def PTX42 : SubtargetFeature<"ptx42", "PTXVersion", "42",
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"Use PTX version 4.2">;
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def PTX43 : SubtargetFeature<"ptx43", "PTXVersion", "43",
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"Use PTX version 4.3">;
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def PTX50 : SubtargetFeature<"ptx50", "PTXVersion", "50",
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"Use PTX version 5.0">;
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def PTX60 : SubtargetFeature<"ptx60", "PTXVersion", "60",
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"Use PTX version 6.0">;
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//===----------------------------------------------------------------------===//
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// NVPTX supported processors.
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//===----------------------------------------------------------------------===//
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class Proc<string Name, list<SubtargetFeature> Features>
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: Processor<Name, NoItineraries, Features>;
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def : Proc<"sm_20", [SM20]>;
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def : Proc<"sm_21", [SM21]>;
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def : Proc<"sm_30", [SM30]>;
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def : Proc<"sm_32", [SM32, PTX40]>;
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def : Proc<"sm_35", [SM35]>;
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def : Proc<"sm_37", [SM37, PTX41]>;
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def : Proc<"sm_50", [SM50, PTX40]>;
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def : Proc<"sm_52", [SM52, PTX41]>;
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def : Proc<"sm_53", [SM53, PTX42]>;
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def : Proc<"sm_60", [SM60, PTX50, SATOM]>;
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def : Proc<"sm_61", [SM61, PTX50, SATOM]>;
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def : Proc<"sm_62", [SM62, PTX50, SATOM]>;
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def : Proc<"sm_70", [SM70, PTX60, SATOM]>;
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def NVPTXInstrInfo : InstrInfo {
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}
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def NVPTX : Target {
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let InstructionSet = NVPTXInstrInfo;
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}
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