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This patch introduces a new pass that computes the safe point to insert the prologue and epilogue of the function. The interest is to find safe points that are cheaper than the entry and exits blocks. As an example and to avoid regressions to be introduce, this patch also implements the required bits to enable the shrink-wrapping pass for AArch64. ** Context ** Currently we insert the prologue and epilogue of the method/function in the entry and exits blocks. Although this is correct, we can do a better job when those are not immediately required and insert them at less frequently executed places. The job of the shrink-wrapping pass is to identify such places. ** Motivating example ** Let us consider the following function that perform a call only in one branch of a if: define i32 @f(i32 %a, i32 %b) { %tmp = alloca i32, align 4 %tmp2 = icmp slt i32 %a, %b br i1 %tmp2, label %true, label %false true: store i32 %a, i32* %tmp, align 4 %tmp4 = call i32 @doSomething(i32 0, i32* %tmp) br label %false false: %tmp.0 = phi i32 [ %tmp4, %true ], [ %a, %0 ] ret i32 %tmp.0 } On AArch64 this code generates (removing the cfi directives to ease readabilities): _f: ; @f ; BB#0: stp x29, x30, [sp, #-16]! mov x29, sp sub sp, sp, #16 ; =16 cmp w0, w1 b.ge LBB0_2 ; BB#1: ; %true stur w0, [x29, #-4] sub x1, x29, #4 ; =4 mov w0, wzr bl _doSomething LBB0_2: ; %false mov sp, x29 ldp x29, x30, [sp], #16 ret With shrink-wrapping we could generate: _f: ; @f ; BB#0: cmp w0, w1 b.ge LBB0_2 ; BB#1: ; %true stp x29, x30, [sp, #-16]! mov x29, sp sub sp, sp, #16 ; =16 stur w0, [x29, #-4] sub x1, x29, #4 ; =4 mov w0, wzr bl _doSomething add sp, x29, #16 ; =16 ldp x29, x30, [sp], #16 LBB0_2: ; %false ret Therefore, we would pay the overhead of setting up/destroying the frame only if we actually do the call. ** Proposed Solution ** This patch introduces a new machine pass that perform the shrink-wrapping analysis (See the comments at the beginning of ShrinkWrap.cpp for more details). It then stores the safe save and restore point into the MachineFrameInfo attached to the MachineFunction. This information is then used by the PrologEpilogInserter (PEI) to place the related code at the right place. This pass runs right before the PEI. Unlike the original paper of Chow from PLDI’88, this implementation of shrink-wrapping does not use expensive data-flow analysis and does not need hack to properly avoid frequently executed point. Instead, it relies on dominance and loop properties. The pass is off by default and each target can opt-in by setting the EnableShrinkWrap boolean to true in their derived class of TargetPassConfig. This setting can also be overwritten on the command line by using -enable-shrink-wrap. Before you try out the pass for your target, make sure you properly fix your emitProlog/emitEpilog/adjustForXXX method to cope with basic blocks that are not necessarily the entry block. ** Design Decisions ** 1. ShrinkWrap is its own pass right now. It could frankly be merged into PEI but for debugging and clarity I thought it was best to have its own file. 2. Right now, we only support one save point and one restore point. At some point we can expand this to several save point and restore point, the impacted component would then be: - The pass itself: New algorithm needed. - MachineFrameInfo: Hold a list or set of Save/Restore point instead of one pointer. - PEI: Should loop over the save point and restore point. Anyhow, at least for this first iteration, I do not believe this is interesting to support the complex cases. We should revisit that when we motivating examples. Differential Revision: http://reviews.llvm.org/D9210 <rdar://problem/3201744> llvm-svn: 236507 |
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.. | ||
InstPrinter | ||
MCTargetDesc | ||
TargetInfo | ||
CMakeLists.txt | ||
LLVMBuild.txt | ||
Makefile | ||
MSP430.h | ||
MSP430.td | ||
MSP430AsmPrinter.cpp | ||
MSP430BranchSelector.cpp | ||
MSP430CallingConv.td | ||
MSP430FrameLowering.cpp | ||
MSP430FrameLowering.h | ||
MSP430InstrFormats.td | ||
MSP430InstrInfo.cpp | ||
MSP430InstrInfo.h | ||
MSP430InstrInfo.td | ||
MSP430ISelDAGToDAG.cpp | ||
MSP430ISelLowering.cpp | ||
MSP430ISelLowering.h | ||
MSP430MachineFunctionInfo.cpp | ||
MSP430MachineFunctionInfo.h | ||
MSP430MCInstLower.cpp | ||
MSP430MCInstLower.h | ||
MSP430RegisterInfo.cpp | ||
MSP430RegisterInfo.h | ||
MSP430RegisterInfo.td | ||
MSP430SelectionDAGInfo.cpp | ||
MSP430SelectionDAGInfo.h | ||
MSP430Subtarget.cpp | ||
MSP430Subtarget.h | ||
MSP430TargetMachine.cpp | ||
MSP430TargetMachine.h | ||
README.txt |
//===---------------------------------------------------------------------===// // MSP430 backend. //===---------------------------------------------------------------------===// DISCLAIMER: Thid backend should be considered as highly experimental. I never seen nor worked with this MCU, all information was gathered from datasheet only. The original intention of making this backend was to write documentation of form "How to write backend for dummies" :) Thes notes hopefully will be available pretty soon. Some things are incomplete / not implemented yet (this list surely is not complete as well): 1. Verify, how stuff is handling implicit zext with 8 bit operands (this might be modelled currently in improper way - should we need to mark the superreg as def for every 8 bit instruction?). 2. Libcalls: multiplication, division, remainder. Note, that calling convention for libcalls is incomptible with calling convention of libcalls of msp430-gcc (these cannot be used though due to license restriction). 3. Implement multiplication / division by constant (dag combiner hook?). 4. Implement non-constant shifts. 5. Implement varargs stuff. 6. Verify and fix (if needed) how's stuff playing with i32 / i64. 7. Implement floating point stuff (softfp?) 8. Implement instruction encoding for (possible) direct code emission in the future. 9. Since almost all instructions set flags - implement brcond / select in better way (currently they emit explicit comparison). 10. Handle imm in comparisons in better way (see comment in MSP430InstrInfo.td) 11. Implement hooks for better memory op folding, etc.