Evandro Menezes c839f35d10 [AArch64] Refactor the Exynos scheduling predicates ... Refactor the scheduling predicates based on `MCInstPredicate`. In this case, for the Exynos processors. Differential revision: https://reviews.llvm.org/D55345 llvm-svn: 348774		2018-12-10 17:17:26 +00:00
..
GlobalISel	[GlobalISel] Use the target preferred type for G_EXTRACT_VECTOR_ELT index.	2018-10-25 14:04:54 +00:00
CodeGenCWrappers.h	[AArch64] Add Tiny Code Model for AArch64	2018-08-22 11:31:39 +00:00
GenericOpcodes.td	[GlobalISel] Add IR translation support for the @llvm.log10 intrinsic	2018-12-07 22:08:02 +00:00
Target.td	[ARM][MC] Move information about variadic register defs into tablegen	2018-12-03 10:32:42 +00:00
TargetCallingConv.td	Remove trailing space	2018-07-30 19:41:25 +00:00
TargetInstrPredicate.td	[AArch64] Refactor the Exynos scheduling predicates	2018-12-10 17:17:26 +00:00
TargetIntrinsicInfo.h
TargetItinerary.td	[NFC] Fix comment of class InstrStage	2018-02-12 15:02:49 +00:00
TargetLoweringObjectFile.h	[MC] Move EH DWARF encodings from MC to CodeGen, NFC	2018-08-09 22:24:04 +00:00
TargetMachine.h	[Targets] Add errors for tiny and kernel codemodel on targets that don't support them	2018-12-07 12:10:23 +00:00
TargetOptions.h	[GlobalISel] Make EnableGlobalISel always set when GISel is enabled	2018-11-29 12:56:32 +00:00
TargetPfmCounters.td	[llvm-exegesis][NFC] Add a way to declare the default counter binding for unbound CPUs for a target.	2018-11-09 13:15:32 +00:00
TargetSchedule.td	[llvm-mca][MC] Add the ability to declare which processor resources model load/store queues (PR36666).	2018-11-29 12:15:56 +00:00
TargetSelectionDAG.td	[DAG] Add fshl/fshr tblgen opcodes	2018-12-05 11:55:33 +00:00