Mikhail Maltsev f7e914e2c5 [ARM][BFloat16] Change types of some Arm and AArch64 bf16 intrinsics ... This patch adjusts the following ARM/AArch64 LLVM IR intrinsics: - neon_bfmmla - neon_bfmlalb - neon_bfmlalt so that they take and return bf16 and float types. Previously these intrinsics used <8 x i8> and <4 x i8> vectors (a rudiment from implementation lacking bf16 IR type). The neon_vbfdot[q] intrinsics are adjusted similarly. This change required some additional selection patterns for vbfdot itself and also for vector shuffles (in a previous patch) because of SelectionDAG transformations kicking in and mangling the original code. This patch makes the generated IR cleaner (less useless bitcasts are produced), but it does not affect the final assembly. Reviewed By: dmgreen Differential Revision: https://reviews.llvm.org/D86146		2020-08-27 18:43:16 +01:00
..
AsmParser	[AArch64][AsmParser] Fix bug in operand printer	2020-08-26 09:31:36 +00:00
Disassembler	[AArch64] Emit warning when disassembling unpredictable LDRAA and LDRAB	2020-06-25 15:56:36 +01:00
GISel	GlobalISel: Add generic instructions for memory intrinsics	2020-08-26 20:08:45 -04:00
MCTargetDesc	[X86][MC][Target] Initial backend support a tune CPU to support -mtune	2020-08-14 15:31:50 -07:00
TargetInfo
Utils	[ARM, AArch64] Fix a comment typo. NFC.	2020-08-06 09:23:45 +03:00
AArch64.h	[AArch64] Extend AArch64SLSHardeningPass to harden BLR instructions.	2020-06-12 07:34:33 +01:00
AArch64.td	[ARM] Add Cortex-A78 and Cortex-X1 Support for Clang and LLVM	2020-07-10 18:24:11 +01:00
AArch64A53Fix835769.cpp
AArch64A57FPLoadBalancing.cpp
AArch64AdvSIMDScalarPass.cpp	[AArch64] Update a code comment incorrectly referring to zero_reg. NFC	2020-08-20 14:36:59 +02:00
AArch64AsmPrinter.cpp	[DebugInfo] Update MachineInstr to help support variadic DBG_VALUE instructions	2020-06-22 16:01:12 +01:00
AArch64BranchTargets.cpp	[AArch64] Fix BTI instruction emission.	2020-06-15 15:04:36 +02:00
AArch64CallingConvention.cpp	[Alignment][NFC] Use Align for TargetCallingConv::OrigAlign	2020-06-25 13:21:22 +00:00
AArch64CallingConvention.h
AArch64CallingConvention.td	[Alignment][NFC] Use Align for TargetCallingConv::OrigAlign	2020-06-25 13:21:22 +00:00
AArch64CleanupLocalDynamicTLSPass.cpp
AArch64CollectLOH.cpp
AArch64Combine.td	[GlobalISel] Add combine for (x & mask) -> x when (x & mask) == x	2020-08-19 10:20:57 -07:00
AArch64CompressJumpTables.cpp
AArch64CondBrTuning.cpp
AArch64ConditionalCompares.cpp	DomTree: Remove getChildren() accessor	2020-07-06 21:58:11 +02:00
AArch64ConditionOptimizer.cpp	MachineBasicBlock::updateTerminator now requires an explicit layout successor.	2020-06-06 22:30:51 -04:00
AArch64DeadRegisterDefinitionsPass.cpp
AArch64ExpandImm.cpp
AArch64ExpandImm.h
AArch64ExpandPseudoInsts.cpp	[SVE] Fix invalid assert in expand_DestructiveOp.	2020-07-04 09:21:40 +00:00
AArch64FalkorHWPFFix.cpp	Prefix some AArch64/ARM passes with "aarch64-"/"arm-"	2020-07-27 11:00:39 -07:00
AArch64FastISel.cpp	AArch64: emit @llvm.debugtrap as brk #0xf000 on all platforms	2020-07-20 10:31:26 +01:00
AArch64FrameLowering.cpp	Reapply D70800: Fix AArch64 AAPCS frame record chain	2020-08-27 17:29:41 +00:00
AArch64FrameLowering.h	[AArch64][SVE] Add missing unwind info for SVE registers.	2020-08-04 11:47:06 +01:00
AArch64GenRegisterBankInfo.def
AArch64InstrAtomics.td
AArch64InstrFormats.td	[ARM][BFloat16] Change types of some Arm and AArch64 bf16 intrinsics	2020-08-27 18:43:16 +01:00
AArch64InstrGISel.td	[AArch64][GlobalISel] Add G_EXT and select ext using it	2020-06-15 12:20:59 -07:00
AArch64InstrInfo.cpp	Reapply D70800: Fix AArch64 AAPCS frame record chain	2020-08-27 17:29:41 +00:00
AArch64InstrInfo.h	[AArch64][SVE] NFC: Rename isOrig -> isReverseInstr	2020-07-02 17:01:15 +01:00
AArch64InstrInfo.td	[ARM][BFloat16] Change types of some Arm and AArch64 bf16 intrinsics	2020-08-27 18:43:16 +01:00
AArch64ISelDAGToDAG.cpp	[SVE] Fix shift-by-imm patterns used by asr, lsl & lsr intrinsics.	2020-08-18 11:41:26 +01:00
AArch64ISelLowering.cpp	[AArch64] Optimize instruction selection for certain vector shuffles	2020-08-27 11:06:49 +01:00
AArch64ISelLowering.h	[AArch64][SVE] Add lowering for llvm fceil	2020-08-26 15:59:44 -04:00
AArch64LoadStoreOptimizer.cpp	[AArch64] Fix ldst-opt of multiple disjunct subregs.	2020-06-08 20:18:24 +01:00
AArch64MachineFunctionInfo.cpp
AArch64MachineFunctionInfo.h	Reapply D70800: Fix AArch64 AAPCS frame record chain	2020-08-27 17:29:41 +00:00
AArch64MacroFusion.cpp
AArch64MacroFusion.h
AArch64MCInstLower.cpp
AArch64MCInstLower.h
AArch64PBQPRegAlloc.cpp
AArch64PBQPRegAlloc.h
AArch64PerfectShuffle.h
AArch64PfmCounters.td
AArch64PromoteConstant.cpp
AArch64RedundantCopyElimination.cpp
AArch64RegisterBanks.td
AArch64RegisterInfo.cpp	[AArch64RegisterInfo] Supress new warning	2020-08-08 21:47:01 +02:00
AArch64RegisterInfo.h	[AArch64][SVE] Disable tail calls if callee does not preserve SVE regs.	2020-08-05 09:38:54 +01:00
AArch64RegisterInfo.td	[AArch64][SVE] Fix CFA calculation in presence of SVE objects.	2020-08-04 11:47:06 +01:00
AArch64SchedA53.td
AArch64SchedA57.td
AArch64SchedA57WriteRes.td
AArch64SchedCyclone.td
AArch64SchedExynosM3.td
AArch64SchedExynosM4.td
AArch64SchedExynosM5.td
AArch64SchedFalkor.td
AArch64SchedFalkorDetails.td
AArch64SchedKryo.td
AArch64SchedKryoDetails.td
AArch64SchedPredExynos.td
AArch64SchedPredicates.td
AArch64SchedThunderX2T99.td
AArch64SchedThunderX3T110.td
AArch64SchedThunderX.td
AArch64Schedule.td
AArch64SelectionDAGInfo.cpp	[CodeGen] Refactor getMemBasePlusOffset & getObjectPtrOffset to accept a TypeSize	2020-08-11 12:17:10 +01:00
AArch64SelectionDAGInfo.h	[Alignment][NFC] Migrate SelectionDAGTargetInfo::EmitTargetCodeForMemset to Align	2020-06-30 12:46:26 +00:00
AArch64SIMDInstrOpt.cpp
AArch64SLSHardening.cpp	[NFC] Clean up uses of MachineModuleInfoWrapperPass	2020-07-01 09:45:05 -07:00
AArch64SpeculationHardening.cpp
AArch64StackOffset.h	[AArch64][SVE] Fix CFA calculation in presence of SVE objects.	2020-08-04 11:47:06 +01:00
AArch64StackTagging.cpp	[ValueTracking] Remove AllocaForValue parameter	2020-07-30 18:48:34 -07:00
AArch64StackTaggingPreRA.cpp
AArch64StorePairSuppress.cpp
AArch64Subtarget.cpp	[X86][MC][Target] Initial backend support a tune CPU to support -mtune	2020-08-14 15:31:50 -07:00
AArch64Subtarget.h	[X86][MC][Target] Initial backend support a tune CPU to support -mtune	2020-08-14 15:31:50 -07:00
AArch64SVEInstrInfo.td	[AArch64][SVE] Add lowering for llvm fceil	2020-08-26 15:59:44 -04:00
AArch64SystemOperands.td
AArch64TargetMachine.cpp	Temporairly revert "[SimplifyCFG][LoopRotate] SimplifyCFG: disable common instruction hoisting by default, enable late in pipeline"	2020-08-22 00:33:22 +03:00
AArch64TargetMachine.h	Support addrspacecast initializers with isNoopAddrSpaceCast	2020-07-31 10:42:43 -04:00
AArch64TargetObjectFile.cpp
AArch64TargetObjectFile.h	[llvm][ELF][AArch64] Handle R_AARCH64_PLT32 relocation	2020-06-10 11:34:16 -07:00
AArch64TargetTransformInfo.cpp	[Analysis] TTI: Add CastContextHint for getCastInstrCost	2020-07-29 13:32:53 +01:00
AArch64TargetTransformInfo.h	[AArch64][SVE] Allow vector of pointers as legal type for masked load/store.	2020-07-31 17:30:23 -07:00
CMakeLists.txt	[AArch64] Introduce AArch64SLSHardeningPass, implementing hardening of RET and BR instructions.	2020-06-11 07:51:17 +01:00
LLVMBuild.txt
SVEInstrFormats.td	[AArch64][SVE] Add lowering for llvm fceil	2020-08-26 15:59:44 -04:00
SVEIntrinsicOpts.cpp	[SVE] Fix bug in SVEIntrinsicOpts::optimizePTest	2020-08-14 07:57:21 +01:00