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llvm-mirror/test/CodeGen/AArch64/framelayout-fp-csr.ll
Owen Anderson 36eea6621c Reapply D70800: Fix AArch64 AAPCS frame record chain
Original Commit Message:
After the commit r368987 (rG643adb55769e) was landed, the frame record (FP and LR register)
may be placed in the middle of a stack frame if a function has both callee-saved
general-purpose registers and floating point registers. This will break the stack unwinders
that simply walk through the frame records (based on the guarantee from AAPCS64
"The Frame Pointer" section). This commit fixes the problem by adding the frame record offset.

Patch By: logan
Differential Revision: D70800
2020-08-27 17:29:41 +00:00

23 lines
802 B
LLVM

; RUN: llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -disable-post-ra --frame-pointer=all < %s | FileCheck %s
; The purpose of this test is to verify that frame pointer (x29)
; is correctly setup in the presence of callee-saved floating
; point registers. The frame pointer should point to the frame
; record, which is located 16 bytes above the end of the CSR
; space when a single FP CSR is in use.
define void @test1(i32) #26 {
entry:
call void asm sideeffect "nop", "~{d8}"() #26
ret void
}
; CHECK-LABEL: test1:
; CHECK: str d8, [sp, #-32]!
; CHECK-NEXT: stp x29, x30, [sp, #16]
; CHECK-NEXT: add x29, sp, #16
; CHECK: nop
; CHECK: ldp x29, x30, [sp, #16]
; CHECK-NEXT: ldr d8, [sp], #32
; CHECK-NEXT: ret
attributes #26 = { nounwind }