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75483b65cd
Summary: Adds the following intrinsics: - faddp - fmaxp, fminp, fmaxnmp & fminnmp - fmlalb, fmlalt, fmlslb & fmlslt - flogb Reviewers: huntergr, sdesmalen, dancgr, efriedma Reviewed By: sdesmalen Subscribers: efriedma, tschuett, kristof.beyls, hiraditya, cameron.mcinally, cfe-commits, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70253
128 lines
5.6 KiB
LLVM
128 lines
5.6 KiB
LLVM
;RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
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;
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; FMLALB (Vectors)
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;
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define <vscale x 4 x float> @fmlalb_h(<vscale x 4 x float> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) {
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; CHECK-LABEL: fmlalb_h:
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; CHECK: fmlalb z0.s, z1.h, z2.h
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x float> @llvm.aarch64.sve.fmlalb.nxv4f32(<vscale x 4 x float> %a,
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<vscale x 8 x half> %b,
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<vscale x 8 x half> %c)
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ret <vscale x 4 x float> %out
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}
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;
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; FMLALB (Indexed)
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;
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define <vscale x 4 x float> @fmlalb_lane_h(<vscale x 4 x float> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) {
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; CHECK-LABEL: fmlalb_lane_h:
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; CHECK: fmlalb z0.s, z1.h, z2.h[0]
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x float> @llvm.aarch64.sve.fmlalb.lane.nxv4f32(<vscale x 4 x float> %a,
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<vscale x 8 x half> %b,
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<vscale x 8 x half> %c,
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i32 0)
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ret <vscale x 4 x float> %out
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}
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;
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; FMLALT (Vectors)
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;
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define <vscale x 4 x float> @fmlalt_h(<vscale x 4 x float> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) {
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; CHECK-LABEL: fmlalt_h:
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; CHECK: fmlalt z0.s, z1.h, z2.h
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x float> @llvm.aarch64.sve.fmlalt.nxv4f32(<vscale x 4 x float> %a,
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<vscale x 8 x half> %b,
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<vscale x 8 x half> %c)
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ret <vscale x 4 x float> %out
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}
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;
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; FMLALT (Indexed)
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;
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define <vscale x 4 x float> @fmlalt_lane_h(<vscale x 4 x float> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) {
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; CHECK-LABEL: fmlalt_lane_h:
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; CHECK: fmlalt z0.s, z1.h, z2.h[1]
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x float> @llvm.aarch64.sve.fmlalt.lane.nxv4f32(<vscale x 4 x float> %a,
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<vscale x 8 x half> %b,
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<vscale x 8 x half> %c,
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i32 1)
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ret <vscale x 4 x float> %out
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}
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;
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; FMLSLB (Vectors)
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;
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define <vscale x 4 x float> @fmlslb_h(<vscale x 4 x float> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) {
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; CHECK-LABEL: fmlslb_h:
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; CHECK: fmlslb z0.s, z1.h, z2.h
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x float> @llvm.aarch64.sve.fmlslb.nxv4f32(<vscale x 4 x float> %a,
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<vscale x 8 x half> %b,
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<vscale x 8 x half> %c)
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ret <vscale x 4 x float> %out
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}
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;
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; FMLSLB (Indexed)
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;
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define <vscale x 4 x float> @fmlslb_lane_h(<vscale x 4 x float> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) {
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; CHECK-LABEL: fmlslb_lane_h:
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; CHECK: fmlslb z0.s, z1.h, z2.h[2]
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x float> @llvm.aarch64.sve.fmlslb.lane.nxv4f32(<vscale x 4 x float> %a,
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<vscale x 8 x half> %b,
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<vscale x 8 x half> %c,
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i32 2)
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ret <vscale x 4 x float> %out
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}
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;
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; FMLSLT (Vectors)
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;
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define <vscale x 4 x float> @fmlslt_h(<vscale x 4 x float> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) {
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; CHECK-LABEL: fmlslt_h:
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; CHECK: fmlslt z0.s, z1.h, z2.h
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x float> @llvm.aarch64.sve.fmlslt.nxv4f32(<vscale x 4 x float> %a,
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<vscale x 8 x half> %b,
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<vscale x 8 x half> %c)
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ret <vscale x 4 x float> %out
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}
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;
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; FMLSLT (Indexed)
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;
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define <vscale x 4 x float> @fmlslt_lane_h(<vscale x 4 x float> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) {
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; CHECK-LABEL: fmlslt_lane_h:
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; CHECK: fmlslt z0.s, z1.h, z2.h[3]
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x float> @llvm.aarch64.sve.fmlslt.lane.nxv4f32(<vscale x 4 x float> %a,
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<vscale x 8 x half> %b,
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<vscale x 8 x half> %c,
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i32 3)
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ret <vscale x 4 x float> %out
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}
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declare <vscale x 4 x float> @llvm.aarch64.sve.fmlalb.nxv4f32(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>)
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declare <vscale x 4 x float> @llvm.aarch64.sve.fmlalb.lane.nxv4f32(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i32)
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declare <vscale x 4 x float> @llvm.aarch64.sve.fmlalt.nxv4f32(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>)
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declare <vscale x 4 x float> @llvm.aarch64.sve.fmlalt.lane.nxv4f32(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i32)
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declare <vscale x 4 x float> @llvm.aarch64.sve.fmlslb.nxv4f32(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>)
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declare <vscale x 4 x float> @llvm.aarch64.sve.fmlslb.lane.nxv4f32(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i32)
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declare <vscale x 4 x float> @llvm.aarch64.sve.fmlslt.nxv4f32(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>)
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declare <vscale x 4 x float> @llvm.aarch64.sve.fmlslt.lane.nxv4f32(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i32)
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