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9d0cca600a
Ensure that load locked and store conditional instructions are only packetized with ALU32 instructions. Patch by Ben Craig. llvm-svn: 279272
13 lines
300 B
LLVM
13 lines
300 B
LLVM
; RUN: llc -march=hexagon < %s
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target triple = "hexagon-unknown--elf"
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; Function Attrs: norecurse nounwind
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define void @_Z4lockv() #0 {
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entry:
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%__shared_owners = alloca i32, align 4
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%0 = cmpxchg weak i32* %__shared_owners, i32 0, i32 1 seq_cst seq_cst
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ret void
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}
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attributes #0 = { nounwind }
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