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5fe828ca5e
This patch issues an error message if Darwin ABI is attempted with the PPC backend. It also cleans up existing test cases, either converting the test to use an alternative triple or removing the test if the coverage is no longer needed. Updated Tests ------------- The majority of test cases were updated to use a different triple that does not include the Darwin ABI. Many tests were also updated to use FileCheck, in place of grep. Deleted Tests ------------- llvm/test/tools/dsymutil/PowerPC/sibling.test was originally added to test specific functionality of dsymutil using an object file created with an old version of llvm-gcc for a Powerbook G4. After a discussion with @JDevlieghere he suggested removing the test. llvm/test/CodeGen/PowerPC/combine_loads_from_build_pair.ll was converted from a PPC test to a SystemZ test, as the behavior is also reproducible there. All other tests that were deleted were specific to the darwin/ppc ABI and no longer necessary. Phabricator Review: https://reviews.llvm.org/D50988 llvm-svn: 340795
87 lines
3.1 KiB
LLVM
87 lines
3.1 KiB
LLVM
; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -verify-machineinstrs -ppc-asm-full-reg-names | FileCheck %s --check-prefix=CHECK --check-prefix=PPC32
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; FIXME: -verify-machineinstrs currently fail on ppc64 (mismatched register/instruction).
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; This is already checked for in Atomics-64.ll
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; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -ppc-asm-full-reg-names | FileCheck %s --check-prefix=CHECK --check-prefix=PPC64
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; In this file, we check that atomic load/store can make use of the indexed
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; versions of the instructions.
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; Indexed version of loads
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define i8 @load_x_i8_seq_cst([100000 x i8]* %mem) {
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; CHECK-LABEL: load_x_i8_seq_cst
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; CHECK: sync
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; CHECK: lbzx [[VAL:r[0-9]+]]
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; CHECK-PPC32: lwsync
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; CHECK-PPC64: cmpw [[CR:cr[0-9]+]], [[VAL]], [[VAL]]
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; CHECK-PPC64: bne- [[CR]], .+4
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; CHECK-PPC64: isync
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%ptr = getelementptr inbounds [100000 x i8], [100000 x i8]* %mem, i64 0, i64 90000
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%val = load atomic i8, i8* %ptr seq_cst, align 1
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ret i8 %val
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}
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define i16 @load_x_i16_acquire([100000 x i16]* %mem) {
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; CHECK-LABEL: load_x_i16_acquire
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; CHECK: lhzx [[VAL:r[0-9]+]]
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; CHECK-PPC32: lwsync
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; CHECK-PPC64: cmpw [[CR:cr[0-9]+]], [[VAL]], [[VAL]]
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; CHECK-PPC64: bne- [[CR]], .+4
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; CHECK-PPC64: isync
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%ptr = getelementptr inbounds [100000 x i16], [100000 x i16]* %mem, i64 0, i64 90000
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%val = load atomic i16, i16* %ptr acquire, align 2
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ret i16 %val
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}
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define i32 @load_x_i32_monotonic([100000 x i32]* %mem) {
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; CHECK-LABEL: load_x_i32_monotonic
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; CHECK: lwzx
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; CHECK-NOT: sync
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%ptr = getelementptr inbounds [100000 x i32], [100000 x i32]* %mem, i64 0, i64 90000
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%val = load atomic i32, i32* %ptr monotonic, align 4
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ret i32 %val
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}
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define i64 @load_x_i64_unordered([100000 x i64]* %mem) {
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; CHECK-LABEL: load_x_i64_unordered
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; PPC32: __sync_
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; PPC64-NOT: __sync_
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; PPC64: ldx
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; CHECK-NOT: sync
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%ptr = getelementptr inbounds [100000 x i64], [100000 x i64]* %mem, i64 0, i64 90000
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%val = load atomic i64, i64* %ptr unordered, align 8
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ret i64 %val
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}
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; Indexed version of stores
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define void @store_x_i8_seq_cst([100000 x i8]* %mem) {
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; CHECK-LABEL: store_x_i8_seq_cst
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; CHECK: sync
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; CHECK: stbx
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%ptr = getelementptr inbounds [100000 x i8], [100000 x i8]* %mem, i64 0, i64 90000
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store atomic i8 42, i8* %ptr seq_cst, align 1
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ret void
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}
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define void @store_x_i16_release([100000 x i16]* %mem) {
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; CHECK-LABEL: store_x_i16_release
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; CHECK: lwsync
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; CHECK: sthx
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%ptr = getelementptr inbounds [100000 x i16], [100000 x i16]* %mem, i64 0, i64 90000
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store atomic i16 42, i16* %ptr release, align 2
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ret void
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}
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define void @store_x_i32_monotonic([100000 x i32]* %mem) {
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; CHECK-LABEL: store_x_i32_monotonic
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; CHECK-NOT: sync
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; CHECK: stwx
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%ptr = getelementptr inbounds [100000 x i32], [100000 x i32]* %mem, i64 0, i64 90000
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store atomic i32 42, i32* %ptr monotonic, align 4
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ret void
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}
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define void @store_x_i64_unordered([100000 x i64]* %mem) {
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; CHECK-LABEL: store_x_i64_unordered
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; CHECK-NOT: sync
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; PPC32: __sync_
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; PPC64-NOT: __sync_
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; PPC64: stdx
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%ptr = getelementptr inbounds [100000 x i64], [100000 x i64]* %mem, i64 0, i64 90000
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store atomic i64 42, i64* %ptr unordered, align 8
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ret void
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}
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