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https://github.com/RPCS3/llvm-mirror.git
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f7cad0a97a
Summary: If we didn't set the value for hasSideEffects bit in our td file, `llvm-tblgen` will set it as true for those instructions which has no match pattern. The instructions `MTLR` and `MFLR` don't set the hasSideEffects flag and don't have match pattern, so their hasSideEffects flag will be set true by `llvm-tblgen`. But in fact, we can use `[LR]` to model the two instructions, so they should not have SideEffects. This patch is to modify the hasSideEffects of MTLR and MFLR from 1 to 0. Reviewed By: jsji Differential Revision: https://reviews.llvm.org/D71390
92 lines
4.2 KiB
LLVM
92 lines
4.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
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; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
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define dso_local signext i32 @caller(i32 signext %a, i32 signext %b, i32 signext %c) local_unnamed_addr {
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; CHECK-LABEL: caller:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: .cfi_def_cfa_offset 192
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: .cfi_offset r14, -144
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; CHECK-NEXT: .cfi_offset r15, -136
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; CHECK-NEXT: .cfi_offset r16, -128
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; CHECK-NEXT: .cfi_offset r17, -120
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; CHECK-NEXT: .cfi_offset r18, -112
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; CHECK-NEXT: .cfi_offset r19, -104
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; CHECK-NEXT: .cfi_offset r20, -96
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; CHECK-NEXT: .cfi_offset r21, -88
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; CHECK-NEXT: .cfi_offset r22, -80
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; CHECK-NEXT: .cfi_offset r23, -72
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; CHECK-NEXT: .cfi_offset r24, -64
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; CHECK-NEXT: .cfi_offset r25, -56
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; CHECK-NEXT: .cfi_offset r26, -48
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; CHECK-NEXT: .cfi_offset r27, -40
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; CHECK-NEXT: .cfi_offset r28, -32
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; CHECK-NEXT: .cfi_offset r29, -24
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; CHECK-NEXT: .cfi_offset r30, -16
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; CHECK-NEXT: .cfi_offset r31, -8
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; CHECK-NEXT: std r14, -144(r1) # 8-byte Folded Spill
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; CHECK-NEXT: std r15, -136(r1) # 8-byte Folded Spill
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; CHECK-NEXT: std r16, -128(r1) # 8-byte Folded Spill
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; CHECK-NEXT: std r17, -120(r1) # 8-byte Folded Spill
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; CHECK-NEXT: std r18, -112(r1) # 8-byte Folded Spill
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; CHECK-NEXT: std r19, -104(r1) # 8-byte Folded Spill
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; CHECK-NEXT: std r20, -96(r1) # 8-byte Folded Spill
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; CHECK-NEXT: std r21, -88(r1) # 8-byte Folded Spill
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; CHECK-NEXT: std r22, -80(r1) # 8-byte Folded Spill
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; CHECK-NEXT: std r23, -72(r1) # 8-byte Folded Spill
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; CHECK-NEXT: std r24, -64(r1) # 8-byte Folded Spill
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; CHECK-NEXT: std r25, -56(r1) # 8-byte Folded Spill
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; CHECK-NEXT: std r26, -48(r1) # 8-byte Folded Spill
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; CHECK-NEXT: std r27, -40(r1) # 8-byte Folded Spill
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; CHECK-NEXT: std r28, -32(r1) # 8-byte Folded Spill
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; CHECK-NEXT: std r29, -24(r1) # 8-byte Folded Spill
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; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
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; CHECK-NEXT: std r31, -8(r1) # 8-byte Folded Spill
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; CHECK-NEXT: std r0, 16(r1)
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; CHECK-NEXT: stdu r1, -192(r1)
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; CHECK-NEXT: std r5, 32(r1) # 8-byte Folded Spill
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; CHECK-NEXT: std r3, 40(r1) # 8-byte Folded Spill
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; CHECK-NEXT: mr r0, r4
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; CHECK-NEXT: ld r3, 40(r1) # 8-byte Folded Reload
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; CHECK-NEXT: #APP
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; CHECK-NEXT: add r3, r3, r0
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: ld r4, 40(r1) # 8-byte Folded Reload
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; CHECK-NEXT: ld r6, 32(r1) # 8-byte Folded Reload
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; CHECK-NEXT: extsw r3, r3
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; CHECK-NEXT: mr r5, r0
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; CHECK-NEXT: bl callee
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; CHECK-NEXT: nop
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; CHECK-NEXT: addi r1, r1, 192
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; CHECK-NEXT: ld r0, 16(r1)
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; CHECK-NEXT: ld r31, -8(r1) # 8-byte Folded Reload
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; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
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; CHECK-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
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; CHECK-NEXT: mtlr r0
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; CHECK-NEXT: ld r28, -32(r1) # 8-byte Folded Reload
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; CHECK-NEXT: ld r27, -40(r1) # 8-byte Folded Reload
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; CHECK-NEXT: ld r26, -48(r1) # 8-byte Folded Reload
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; CHECK-NEXT: ld r25, -56(r1) # 8-byte Folded Reload
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; CHECK-NEXT: ld r24, -64(r1) # 8-byte Folded Reload
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; CHECK-NEXT: ld r23, -72(r1) # 8-byte Folded Reload
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; CHECK-NEXT: ld r22, -80(r1) # 8-byte Folded Reload
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; CHECK-NEXT: ld r21, -88(r1) # 8-byte Folded Reload
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; CHECK-NEXT: ld r20, -96(r1) # 8-byte Folded Reload
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; CHECK-NEXT: ld r19, -104(r1) # 8-byte Folded Reload
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; CHECK-NEXT: ld r18, -112(r1) # 8-byte Folded Reload
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; CHECK-NEXT: ld r17, -120(r1) # 8-byte Folded Reload
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; CHECK-NEXT: ld r16, -128(r1) # 8-byte Folded Reload
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; CHECK-NEXT: ld r15, -136(r1) # 8-byte Folded Reload
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; CHECK-NEXT: ld r14, -144(r1) # 8-byte Folded Reload
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; CHECK-NEXT: blr
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entry:
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%0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13}"(i32 %a, i32 %b)
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%call = tail call signext i32 @callee(i32 signext %0, i32 signext %a, i32 signext %b, i32 signext %c)
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ret i32 %call
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}
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declare signext i32 @callee(i32 signext, i32 signext, i32 signext, i32 signext) local_unnamed_addr
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